Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link
14	P. N. Bibilo	The use of models of incompletely specified Boolean functions in logical circuit synthesis based on VHDL descriptions.	Autom. Control. Comput. Sci.	2013	DBLP DOI BibTeX RDF
14	Wassim Mansour, Raoul Velazco	SEU Fault-Injection in VHDL-Based Processors: A Case Study.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
14	Mohamed Azim Mohamed	FPGA Synthesis of VHDL OFDM System.	Wirel. Pers. Commun.	2013	DBLP DOI BibTeX RDF
14	Vacius Jusas, Tomas Neverdauskas	Combining Software and Hardware Test Generation Methods to Verify VHDL Models.	Inf. Technol. Control.	2013	DBLP DOI BibTeX RDF
14	Godofredo R. Garay, Julio Ortega Lopera, Antonio F. Díaz, Luis Corrales, Vicente Alarcón Aquino	System performance evaluation by combining RTC and VHDL simulation: A case study on NICs.	J. Syst. Archit.	2013	DBLP DOI BibTeX RDF
14	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	Extensible open-source framework for translating RTL VHDL IP cores to SystemC.	DDECS	2013	DBLP DOI BibTeX RDF
14	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu	Performance analysis of cosimulating processor core in VHDL and SystemC.	ICACCI	2013	DBLP DOI BibTeX RDF
14	Jean-Marie Gauthier, Fabrice Bouquet, Ahmed Hammad, Fabien Peureux	Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS.	MODELSWARD	2013	DBLP DOI BibTeX RDF
14	Wieslaw Marszalek, Michal Melosik	Circuits with mixed mode oscillations in VHDL-AMS.	MWSCAS	2013	DBLP DOI BibTeX RDF
14	Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi	Extracting complete set of equations to analyze VHDL-AMS descriptions.	EWDTS	2013	DBLP DOI BibTeX RDF
14	Dmitry A. Velychko, Iegor I. Vdovychenko	The evaluation of statistical characteristics of the retransmission meter signal frequency and initial phase on the basis of VHDL-model.	EWDTS	2013	DBLP DOI BibTeX RDF
14	Dmitry I. Cheremisinov	Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration.	EWDTS	2013	DBLP DOI BibTeX RDF
14	Sergey Ostroumov, Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila	Generation of Structural VHDL Code with Library Components from Formal Event-B Models.	DSD	2013	DBLP DOI BibTeX RDF
14	Siham Hairoud, Tristan Dubois, Angelique Tetelin, Geneviève Duchamp	Conducted immunity of three Op-Amps using the DPI measurement technique and VHDL-AMS modeling.	EMC Compo	2013	DBLP DOI BibTeX RDF
14	Simen Gimle Hansen, Dirk Koch, Jim Tørresen	Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL.	ReCoSoC	2013	DBLP DOI BibTeX RDF
14	James Shueyen Tai, Kin Fun Li, Haytham Elmiligi	Dynamic Time Warping Algorithm: A Hardware Realization in VHDL.	ICITCS	2013	DBLP DOI BibTeX RDF
14	Ahmed A. Rezk, Amr Helmy, Ahmed Abdallah, Yehea Ismail	VHDL implementation of Maximum Power Point Tracking algorithms.	ICECS	2013	DBLP DOI BibTeX RDF
14	Fernando Pereira, Luís Gomes 0001	Automatic synthesis of VHDL hardware components from IOPT Petri net models.	IECON	2013	DBLP DOI BibTeX RDF
14	Chi-Pan Hwang, Mu-Song Chen	The UML Diagram to VHDL Code Transformation Based on MDA Methodology.	ICSI (2)	2013	DBLP DOI BibTeX RDF
14	Vacius Jusas, Tomas Neverdauskas	Novel Method to Generate Tests for VHDL.	ICIST	2013	DBLP DOI BibTeX RDF
14	Stefan Potyra	Transparente und hochperformante VHDL-Cosimulation im Kontext der virtuellen Maschine FAUmachine.		2013	RDF
14	Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki	System level modeling methodology of NoC design from UML-MARTE to VHDL.	Des. Autom. Embed. Syst.	2012	DBLP DOI BibTeX RDF
14	Sliman Arrag, Abdellatif Hamdoun, Abderrahim Tragha, Salah eddine Khamlich	Several AES Variants under VHDL language In FPGA	CoRR	2012	DBLP BibTeX RDF
14	Michael Schmidt 0004, Marc Reichenbach, Dietmar Fey	A Generic VHDL Template for 2D Stencil Code Applications on FPGAs.	ISORC Workshops	2012	DBLP DOI BibTeX RDF
14	Emad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi	Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis.	DSD	2012	DBLP DOI BibTeX RDF
14	Razvan Nane, Vlad Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova, Koen Bertels	DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler.	FPL	2012	DBLP DOI BibTeX RDF
14	Quentin Beraud-Sudreau, Olivier Mazouffre, Michel Pignol, Louis Baguena, Claude Neveu, Jean-Baptiste Bégueret, Thierry Taris	VHDL-AMS model of an injection locked VCO.	NEWCAS	2012	DBLP DOI BibTeX RDF
14	Todd E. Schmuland, Mohsin M. Jamali, Matthew B. Longbrake, Peter E. Buxa	CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation.	NEWCAS	2012	DBLP DOI BibTeX RDF
14	Emna Kallel, Yassine Aoudni, Mohamed Abid	Automatic generation of Coprocessor program from VHDL description.	MECO	2012	DBLP BibTeX RDF
14	Arjuna Madanayake, Chamith Wijenayake, Rimesh M. Joshi, Jim Grover, Joan Carletta, Jay L. Adams, Tom T. Hartley, Tokunbo Ogunfunmi	Teaching freshmen VHDL-based digital design.	ISCAS	2012	DBLP DOI BibTeX RDF
14	Yann Thoma, Etienne Messerli, Michel Starkier, Daniel Molla, Sebastien Masle, Christophe Bianchi, Oliver Gubler, Claude Magliocco, Philippe Crausaz, Samuel Tache, Denis Prêtre, Gregory Trolliet	Math2Mat: From Octave/Matlab to VHDL.	AHS	2012	DBLP DOI BibTeX RDF
14	Nikolaos Kavvadias, Kostas Masselos	Design of fixed-point rounding operators for the VHDL-2008 standard.	DASIP	2012	DBLP BibTeX RDF
14	Wassim Mansour, Raoul Velazco	SEU fault-injection in VHDL-based processors: A case study.	LATW	2012	DBLP DOI BibTeX RDF
14	Doru Todinca, Daniel Butoianu	VHDL Framework for Modeling Fuzzy Automata.	SYNASC	2012	DBLP DOI BibTeX RDF
14	Vacius Jusas, Tomas Neverdauskas	FSM Based Functional Test Generation Framework for VHDL.	ICIST	2012	DBLP DOI BibTeX RDF
14	Sven Slawinski, Lutz Zacharias, Mirko Bodach, Thomas Hempel, Björn Veit	Design flow optimization for controller electronics in alternative electrical power systems using VHDL-AMS.	SSD	2012	DBLP DOI BibTeX RDF
14	Jacobo Álvarez, Óscar Lopez, Francisco D. Freijedo, Jesús Doval-Gandoy	Digital Parameterizable VHDL Module for Multilevel Multiphase Space Vector PWM.	IEEE Trans. Ind. Electron.	2011	DBLP DOI BibTeX RDF
14	Julian A. Bailey, Reuben Wilcock, Peter R. Wilson, John E. Chad	Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL.	Neurocomputing	2011	DBLP DOI BibTeX RDF
14	Antonio García Dopico, Antonio Pérez, Santiago Rodríguez, Maria Isabel García	A New Algorithm for VHDL Parallel Simulation.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
14	Roberto Sepúlveda, Oscar Montiel, Oscar Castillo 0001, Patricia Melin	Modelling and Simulation of the defuzzification Stage of a Type-2 Fuzzy Controller Using VHDL Code.	Control. Intell. Syst.	2011	DBLP DOI BibTeX RDF
14	Jun Cheng	Design of high-precision FFT based on VHDL and analysis of code coverage.	EMEIT	2011	DBLP DOI BibTeX RDF
14	Manuel Rivas Pérez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Arturo Morgado Estevez, Antón Civit, Gabriel Jiménez	An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata.	IWANN (1)	2011	DBLP DOI BibTeX RDF
14	Erica Jones, Jonathan Sprinkle	autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers.	SPLASH Workshops	2011	DBLP DOI BibTeX RDF
14	Sergey Ostroumov, Leonidas Tsiopoulos	VHDL Code Generation from Formal Event-B Models.	DSD	2011	DBLP DOI BibTeX RDF
14	Marcus R. Perrett, Izzat Darwazeh	A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic Reconfigurability.	ReConFig	2011	DBLP DOI BibTeX RDF
14	Otavio de Souza Martins Gomes, Robson L. Moreno, Tales Cleber Pimenta	A fast cryptography pipelined hardware developed in FPGA with VHDL.	ICUMT	2011	DBLP BibTeX RDF
14	Anita Ratna Dewi Susanti, Wildan Thoyib, Thomas Schumann	Development of a reliable GUI for DiaHDL: A web-based VHDL code generator.	ICEEI	2011	DBLP DOI BibTeX RDF
14	Thomas Schumann, Anita Ratna Dewi Susanti	FPGA design for image processing using a GUI of a web-based VHDL Code Generator.	VCIP	2011	DBLP DOI BibTeX RDF
14	Philip I. Necsulescu, Voicu Groza	Automatic generation of VHDL hardware code from data flow graphs.	SACI	2011	DBLP DOI BibTeX RDF
14	Gatis Valters	Initial version of Matlab/Simulink based tool for VHDL code generation and FPGA implementation of Elementary Generalized Unitary rotation.	NORCHIP	2011	DBLP DOI BibTeX RDF
14	Mahmoud Fawzy Wagdy, Anurag Nannaka, Rajeev K. N. Channegowda	A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations.	ITNG	2011	DBLP DOI BibTeX RDF
14	Jana Flochova, Jakub Holly, Michal Zapaticky, Ján Pivarcek	Model based implementation of supervisors and diagnosers in VHDL code of programmable systems.	EUROCON	2011	DBLP DOI BibTeX RDF
14	Dominik Macko, Katarína Jelemenská	VHDL structural model visualization.	EUROCON	2011	DBLP DOI BibTeX RDF
14	Ime J. Umoh, Tom J. Kazmierski	VHDL-AMS model of a dual gate graphene FET.	FDL	2011	DBLP BibTeX RDF
14	Ivan Shcherbakov, Christian Weis, Norbert Wehn	Bringing C++ productivity to VHDL world: From language definition to a case study.	FDL	2011	DBLP BibTeX RDF
14	Zbynek Fedra, Jaromir Kolouch	VHDL procedure for combinational divider.	TSP	2011	DBLP DOI BibTeX RDF
14	Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song	Design and verification of an application-specific PLD using VHDL and SystemVerilog.	ASICON	2011	DBLP DOI BibTeX RDF
14	Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton	Enhancing ABC for stabilization verification of SystemVerilog/VHDL models.	DIFTS@FMCAD	2011	DBLP BibTeX RDF
14	Paramjot Saini, Mandeep Singh, Balwinder Singh	VHDL Implementation of PCI Bus Arbiter Using Arbitration Algorithms.	IC3	2011	DBLP DOI BibTeX RDF
14	Milind Khanapurkar, Jayant Y. Hande, Preeti R. Bajaj	Approach for VHDL and FPGA Implementation of Communication Controller of FlexRay Controller.	J. Inf. Hiding Multim. Signal Process.	2010	DBLP BibTeX RDF
14	Francisco J. Azcondo, Angel de Castro, Christian Brañas	Course on Digital Electronics Oriented to Describing Systems in VHDL.	IEEE Trans. Ind. Electron.	2010	DBLP DOI BibTeX RDF
14	Isidoro Urriza, Luis Angel Barragan, Denis Navarro, José Ignacio Artigas, Oscar Lucía	Word Length Selection Method for Controller Implementation on FPGAs Using the VHDL-2008 Fixed-Point and Floating-Point Packages.	EURASIP J. Embed. Syst.	2010	DBLP DOI BibTeX RDF
14	David O'Sullivan, Donal Heffernan	VHDL architecture for IEC 61499 function blocks.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
14	Akash Kumar Gupta, Sanjeet Kumar	VHDL Implementation of different Turbo Encoder using Log-MAP Decoder	CoRR	2010	DBLP BibTeX RDF
14	M. Kamaraju, A. V. N. Tilak, K. Lal Kishore, K. Baburao	VHDL Implementation and Verification of ARINC-429 Core	CoRR	2010	DBLP BibTeX RDF
14	Oana Boncalo, Alexandru Amaricai, Mihai Udrescu, Mircea Vladutiu	Quantum circuit's reliability assessment with VHDL-based simulated fault injection.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
14	Roberto d'Amore	A Synthesis-Oriented VHDL Course.	ACM Trans. Comput. Educ.	2010	DBLP DOI BibTeX RDF
14	Eladio Gutiérrez, María A. Trenas, Julián Ramos, Francisco Corbera, Sergio Romero 0001	A new Moodle module supporting automatic verification of VHDL-based assignments.	Comput. Educ.	2010	DBLP DOI BibTeX RDF
14	Ali Hayek, Michael Schreiber, Josef Börcsök	Basic VHDL tests conforming to IEC 61508.	INSS	2010	DBLP DOI BibTeX RDF
14	Sergey Mikhtonyuk, Maksim Davydov, Roman Hwang, Dmitry Shcherbin	IEEE 1500 compliant test wrapper generation tool for VHDL models.	EWDTS	2010	DBLP DOI BibTeX RDF
14	Manfred Dietrich, Uwe Eichler, Joachim Haase	Digital statistical analysis using VHDL.	DATE	2010	DBLP DOI BibTeX RDF
14	Shaila Subbaraman, Manish M. Patil, Prashant S. Nilkund	Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code.	ICARCV	2010	DBLP DOI BibTeX RDF
14	Tolga Ayav, Tugkan Tuglular, Fevzi Belli	Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker.	SSIRI (Companion)	2010	DBLP DOI BibTeX RDF
14	Cédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, Slavisa Jovanovic	Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education.	ReCoSoC	2010	DBLP BibTeX RDF
14	Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef	Verification of a VHDL GPS baseband processor using a simulink-based test bench generator.	ICECS	2010	DBLP DOI BibTeX RDF
14	Nicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt, Ivan Grech	VHDL implemetation of a DMX512 decoder on a FPGA.	ICECS	2010	DBLP DOI BibTeX RDF
14	Sahbi Baccar, Timothée Levi, Dominique Dallet, Vladimir Shitikov, François Barbara	A behavioral and temperature measurements-based modeling of an operational amplifier using VHDL-AMS.	ICECS	2010	DBLP DOI BibTeX RDF
14	Stefan Potyra, Matthias Sand, Volkmar Sieh, Dietmar Fey	Seamless high speed simulation of VHDL components in the context of comprehensive computing systems using the virtual machine faumachine.	WSC	2010	DBLP DOI BibTeX RDF
14	Jimmy Xu, Nikhil Subramanian, Adam M. Alessio, Scott Hauck	Impulse C vs. VHDL for Accelerating Tomographic Reconstruction.	FCCM	2010	DBLP DOI BibTeX RDF
14	Charles André, Frédéric Mallet, Julien DeAntoni	VHDL Observers for Clock Constraint Checking.	SIES	2010	DBLP DOI BibTeX RDF
14	Stefan Hauser	Entwurf eines generischen, applikationsspezifischen, transportgesteuerten Prozessor-Modells in VHDL und Validierung auf einem FPGA.	Informatiktage	2010	DBLP BibTeX RDF
14	Marie Rouvière, Emmanuelle Bourdel, Sébastien Quintanel, Bertrand Granado	VHDL-AMS model of RF-Interconnect System for Global On-Chip Communication.	FDL	2010	DBLP BibTeX RDF
14	Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault	Formal Verification of Timed VHDL Programs.	FDL	2010	DBLP BibTeX RDF
14	Bharati B. Sayankar, P. H. Rangaree, S. D. Giripunje	Filtering of Images by Kalman Filter Using VHDL.	ICETET	2010	DBLP DOI BibTeX RDF
14	Prachi Rane	Design of Modbus Controller Using VHDL for Remote Administrations of a Network of Devices.	ICETET	2010	DBLP DOI BibTeX RDF
14	Abdulhadi Shoufan	A compact course on VHDL-AMS.	ISCAS	2010	DBLP DOI BibTeX RDF
14	Tomás G. Moreira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Jean-François Pétin, Eric Levrat	Generating VHDL Source Code from UML Models of Embedded Systems.	DIPES/BICC	2010	DBLP DOI BibTeX RDF
14	John M. Espinosa-Duran, Vladimir Trujillo-Olaya, Jaime Velasco-Medina, Raoul Velazco	Bit-flip injection strategies for FSMs modeled in VHDL behavioral level.	LATW	2010	DBLP DOI BibTeX RDF
14	Mary M. Randolph-Gips	Metabolic Pathways Modeling using VHDL-AMS.	BICoB	2010	DBLP BibTeX RDF
14	Julian A. Bailey	Towards the neurocomputer : an investigation of VHDL neuron models.		2010	RDF
14	Leran Wang, Tom J. Kazmierski	VHDL-AMS Based Genetic Optimization of Mixed-Physical-Domain Systems in Automotive Applications.	Simul.	2009	DBLP DOI BibTeX RDF
14	Christopher Pohl, Carlos Paiz, Mario Porrmann	vMAGIC - Automatic Code Generation for VHDL.	Int. J. Reconfigurable Comput.	2009	DBLP DOI BibTeX RDF
14	Takialddin Al-smadi	Learning to Computer Architecture Courses Using Verilog Hardware Description Language (VHDL).	Egypt. Comput. Sci. J.	2009	DBLP BibTeX RDF
14	Silvano R. Rossi, Edward David Moreno, Aparecido Augusto de Carvalho, Alexandre C. R. da Silva, Edson Antonio Batista, Thiago Alexandre Prado, Tércio A. Santos Filho	A VHDL-based protocol controller for NCAP processors.	Comput. Stand. Interfaces	2009	DBLP DOI BibTeX RDF
14	Martin Schubert	An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
14	Roberto Sepúlveda, Oscar Montiel, José Angel Olivas, Oscar Castillo 0001	Methodology to Test and Validate a VHDL Inference Engine of a Type-2 FIS, through the Xilinx System Generator.	Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control	2009	DBLP DOI BibTeX RDF
14	Rohit Sharma, Vivek Kumar Sehgal, Nitin 0001, Pranav Bhasker, Ishita Verma	Design and Implementation of a 64-bit RISC Processor Using VHDL.	UKSim	2009	DBLP DOI BibTeX RDF
14	Lixin Cheng, Jinian Bian, Yunyun Liu	An approach to synthesis delay semantics in VHDL.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
14	Shadi Moazzeni, Saadat Poormozaffari, Amin Emami	An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage.	MTV	2009	DBLP DOI BibTeX RDF
14	Sven Slawinski, Lutz Zacharias, Robert Dorn, Johann Hauer	Erstellung und Verifizierung eines VHDL-AMS-Modells für einen kapazitiven Delta-Sigma-Modulator.	MBMV	2009	DBLP BibTeX RDF