Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | P. N. Bibilo |
The use of models of incompletely specified Boolean functions in logical circuit synthesis based on VHDL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. Control. Comput. Sci. ![In: Autom. Control. Comput. Sci. 47(3), pp. 122-131, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Wassim Mansour, Raoul Velazco |
SEU Fault-Injection in VHDL-Based Processors: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 29(1), pp. 87-94, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Mohamed Azim Mohamed |
FPGA Synthesis of VHDL OFDM System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 70(4), pp. 1885-1909, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Vacius Jusas, Tomas Neverdauskas |
Combining Software and Hardware Test Generation Methods to Verify VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Technol. Control. ![In: Inf. Technol. Control. 42(4), pp. 362-368, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Godofredo R. Garay, Julio Ortega Lopera, Antonio F. Díaz, Luis Corrales, Vicente Alarcón Aquino |
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 59(10-D), pp. 1277-1298, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Syed Saif Abrar, Maksim Jenihhin, Jaan Raik |
Extensible open-source framework for translating RTL VHDL IP cores to SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, pp. 112-115, 2013, IEEE Computer Society, 978-1-4673-6135-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu |
Performance analysis of cosimulating processor core in VHDL and SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: International Conference on Advances in Computing, Communications and Informatics, ICACCI 2013, Mysore, India, August 22-25, 2013, pp. 563-568, 2013, IEEE, 978-1-4799-2432-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Jean-Marie Gauthier, Fabrice Bouquet, Ahmed Hammad, Fabien Peureux |
Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MODELSWARD ![In: MODELSWARD 2013 - Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development, Barcelona, Spain, 19 - 21 February, 2013, pp. 123-128, 2013, SciTePress, 978-989-8565-42-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Wieslaw Marszalek, Michal Melosik |
Circuits with mixed mode oscillations in VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 149-152, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi |
Extracting complete set of equations to analyze VHDL-AMS descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Dmitry A. Velychko, Iegor I. Vdovychenko |
The evaluation of statistical characteristics of the retransmission meter signal frequency and initial phase on the basis of VHDL-model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Dmitry I. Cheremisinov |
Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Sergey Ostroumov, Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila |
Generation of Structural VHDL Code with Library Components from Formal Event-B Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 111-118, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Siham Hairoud, Tristan Dubois, Angelique Tetelin, Geneviève Duchamp |
Conducted immunity of three Op-Amps using the DPI measurement technique and VHDL-AMS modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMC Compo ![In: 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2013, Nara, Japan, December 15-18, 2013, pp. 53-58, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Simen Gimle Hansen, Dirk Koch, Jim Tørresen |
Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013, pp. 1-8, 2013, IEEE, 978-1-4673-6180-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | James Shueyen Tai, Kin Fun Li, Haytham Elmiligi |
Dynamic Time Warping Algorithm: A Hardware Realization in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICITCS ![In: 2013 International Conference on IT Convergence and Security, ICITCS 2013, Macau, China, December 16-18, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2845-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Ahmed A. Rezk, Amr Helmy, Ahmed Abdallah, Yehea Ismail |
VHDL implementation of Maximum Power Point Tracking algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 389-392, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Fernando Pereira, Luís Gomes 0001 |
Automatic synthesis of VHDL hardware components from IOPT Petri net models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, Vienna, Austria, November 10-13, 2013, pp. 2214-2219, 2013, IEEE, 978-1-4799-0224-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Chi-Pan Hwang, Mu-Song Chen |
The UML Diagram to VHDL Code Transformation Based on MDA Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSI (2) ![In: Advances in Swarm Intelligence, 4th International Conference, ICSI 2013, Harbin, China, June 12-15, 2013, Proceedings, Part II, pp. 496-503, 2013, Springer, 978-3-642-38714-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Vacius Jusas, Tomas Neverdauskas |
Novel Method to Generate Tests for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIST ![In: Information and Software Technologies - 19th International Conference, ICIST 2013, Kaunas, Lithuania, October 2013. Proceedings, pp. 365-375, 2013, Springer, 978-3-642-41946-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Stefan Potyra |
Transparente und hochperformante VHDL-Cosimulation im Kontext der virtuellen Maschine FAUmachine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
14 | Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki |
System level modeling methodology of NoC design from UML-MARTE to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 16(4), pp. 161-187, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Sliman Arrag, Abdellatif Hamdoun, Abderrahim Tragha, Salah eddine Khamlich |
Several AES Variants under VHDL language In FPGA ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1210.4962, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
14 | Michael Schmidt 0004, Marc Reichenbach, Dietmar Fey |
A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC Workshops ![In: 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORC Workshops 2012, Shenzhen, China, April 11, 2012, pp. 180-187, 2012, IEEE Computer Society, 978-1-4673-0900-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Emad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi |
Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012, pp. 708-714, 2012, IEEE Computer Society, 978-1-4673-2498-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Razvan Nane, Vlad Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova, Koen Bertels |
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 619-622, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Quentin Beraud-Sudreau, Olivier Mazouffre, Michel Pignol, Louis Baguena, Claude Neveu, Jean-Baptiste Bégueret, Thierry Taris |
VHDL-AMS model of an injection locked VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 10th IEEE International NEWCAS Conference, Montreal, QC, Canada, June 17-20, 2012, pp. 25-28, 2012, IEEE, 978-1-4673-0857-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Todd E. Schmuland, Mohsin M. Jamali, Matthew B. Longbrake, Peter E. Buxa |
CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 10th IEEE International NEWCAS Conference, Montreal, QC, Canada, June 17-20, 2012, pp. 237-240, 2012, IEEE, 978-1-4673-0857-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Emna Kallel, Yassine Aoudni, Mohamed Abid |
Automatic generation of Coprocessor program from VHDL description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 1st Mediterranean Conference on Embedded Computing, MECO 2012, Bar, Montenegro, June 19-21, 2012, pp. 34-37, 2012, IEEE. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
14 | Arjuna Madanayake, Chamith Wijenayake, Rimesh M. Joshi, Jim Grover, Joan Carletta, Jay L. Adams, Tom T. Hartley, Tokunbo Ogunfunmi |
Teaching freshmen VHDL-based digital design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 2701-2704, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Yann Thoma, Etienne Messerli, Michel Starkier, Daniel Molla, Sebastien Masle, Christophe Bianchi, Oliver Gubler, Claude Magliocco, Philippe Crausaz, Samuel Tache, Denis Prêtre, Gregory Trolliet |
Math2Mat: From Octave/Matlab to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2012, Erlangen, Germany, June 25-28, 2012, pp. 264-271, 2012, IEEE, 978-1-4673-1915-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Nikolaos Kavvadias, Kostas Masselos |
Design of fixed-point rounding operators for the VHDL-2008 standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, DASIP 2012, Karlsruhe, Germany, October 23-25, 2012, pp. 1-8, 2012, IEEE, 978-1-4673-2089-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
14 | Wassim Mansour, Raoul Velazco |
SEU fault-injection in VHDL-based processors: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 13th Latin American Test Workshop, LATW 2012, Quito, Ecuador, April 10-13, 2012, pp. 1-5, 2012, IEEE Computer Society, 978-1-4673-2355-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Doru Todinca, Daniel Butoianu |
VHDL Framework for Modeling Fuzzy Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: 14th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2012, Timisoara, Romania, September 26-29, 2012, pp. 171-178, 2012, IEEE Computer Society, 978-1-4673-5026-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Vacius Jusas, Tomas Neverdauskas |
FSM Based Functional Test Generation Framework for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIST ![In: Information and Software Technologies - 18th International Conference, ICIST 2012, Kaunas, Lithuania, September 13-14, 2012. Proceedings, pp. 138-148, 2012, Springer, 978-3-642-33307-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Sven Slawinski, Lutz Zacharias, Mirko Bodach, Thomas Hempel, Björn Veit |
Design flow optimization for controller electronics in alternative electrical power systems using VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: International Multi-Conference on Systems, Signals & Devices, SSD 2012, Chemnitz, Germany, March 20-23, 2012, pp. 1-3, 2012, IEEE, 978-1-4673-1590-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Jacobo Álvarez, Óscar Lopez, Francisco D. Freijedo, Jesús Doval-Gandoy |
Digital Parameterizable VHDL Module for Multilevel Multiphase Space Vector PWM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 58(9), pp. 3946-3957, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Julian A. Bailey, Reuben Wilcock, Peter R. Wilson, John E. Chad |
Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 74(14-15), pp. 2392-2406, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Antonio García Dopico, Antonio Pérez, Santiago Rodríguez, Maria Isabel García |
A New Algorithm for VHDL Parallel Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 16(3), pp. 27:1-27:31, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Roberto Sepúlveda, Oscar Montiel, Oscar Castillo 0001, Patricia Melin |
Modelling and Simulation of the defuzzification Stage of a Type-2 Fuzzy Controller Using VHDL Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Control. Intell. Syst. ![In: Control. Intell. Syst. 39(1), 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Jun Cheng |
Design of high-precision FFT based on VHDL and analysis of code coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMEIT ![In: International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, Harbin, Heilongjiang, China, 12-14 August, 2011, pp. 3579-3582, 2011, IEEE, 978-1-61284-087-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Manuel Rivas Pérez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Arturo Morgado Estevez, Antón Civit, Gabriel Jiménez |
An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (1) ![In: Advances in Computational Intelligence - 11th International Work-Conference on Artificial Neural Networks, IWANN 2011, Torremolinos-Málaga, Spain, June 8-10, 2011, Proceedings, Part I, pp. 157-165, 2011, Springer, 978-3-642-21500-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Erica Jones, Jonathan Sprinkle |
autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLASH Workshops ![In: SPLASH'11 Workshops - Compilation Proceedings of the Co-Located Workshops: DSM'11, TMC'11, AGERE!'11, AOOPES'11, NEAT'11, and VMIL'11, Portland, OR, USA, October 22-27, 2011, pp. 71-76, 2011, ACM, 978-1-4503-1183-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Sergey Ostroumov, Leonidas Tsiopoulos |
VHDL Code Generation from Formal Event-B Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 127-134, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Marcus R. Perrett, Izzat Darwazeh |
A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic Reconfigurability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011, pp. 286-290, 2011, IEEE Computer Society, 978-1-4577-1734-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Otavio de Souza Martins Gomes, Robson L. Moreno, Tales Cleber Pimenta |
A fast cryptography pipelined hardware developed in FPGA with VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUMT ![In: 3rd International Congress on Ultra Modern Telecommunications and Control Systems and Workshops, ICUMT 2011, Budapest, Hungary, October 5-7, 2011, pp. 1-6, 2011, IEEE, 978-1-4577-0682-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
14 | Anita Ratna Dewi Susanti, Wildan Thoyib, Thomas Schumann |
Development of a reliable GUI for DiaHDL: A web-based VHDL code generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEEI ![In: International Conference on Electrical Engineering and Informatics, ICEEI 2011, Bandung, Indonesia, 17-19 July, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-0753-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Thomas Schumann, Anita Ratna Dewi Susanti |
FPGA design for image processing using a GUI of a web-based VHDL Code Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VCIP ![In: 2011 IEEE Visual Communications and Image Processing, VCIP 2011, Tainan, Taiwan, November 6-9, 2011, pp. 1, 2011, IEEE, 978-1-4577-1321-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Philip I. Necsulescu, Voicu Groza |
Automatic generation of VHDL hardware code from data flow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SACI ![In: 6th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI, 2011, Timisoara, Romania, May 19-21, 2011, pp. 523-528, 2011, IEEE, 978-1-4244-9108-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Gatis Valters |
Initial version of Matlab/Simulink based tool for VHDL code generation and FPGA implementation of Elementary Generalized Unitary rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-6, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Mahmoud Fawzy Wagdy, Anurag Nannaka, Rajeev K. N. Channegowda |
A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Eighth International Conference on Information Technology: New Generations, ITNG 2011, Las Vegas, Nevada, USA, 11-13 April 2011, pp. 777-784, 2011, IEEE Computer Society, 978-0-7695-4367-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Jana Flochova, Jakub Holly, Michal Zapaticky, Ján Pivarcek |
Model based implementation of supervisors and diagnosers in VHDL code of programmable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: Proceedings of EUROCON 2011, International Conference on Computer as a Tool, 27-29 April 2011, Lisbon, Portugal, pp. 1-4, 2011, IEEE. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Dominik Macko, Katarína Jelemenská |
VHDL structural model visualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: Proceedings of EUROCON 2011, International Conference on Computer as a Tool, 27-29 April 2011, Lisbon, Portugal, pp. 1-4, 2011, IEEE. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Ime J. Umoh, Tom J. Kazmierski |
VHDL-AMS model of a dual gate graphene FET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-0763-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
14 | Ivan Shcherbakov, Christian Weis, Norbert Wehn |
Bringing C++ productivity to VHDL world: From language definition to a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, pp. 1-7, 2011, IEEE, 978-1-4577-0763-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
14 | Zbynek Fedra, Jaromir Kolouch |
VHDL procedure for combinational divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TSP ![In: 34th International Conference on Telecommunications and Signal Processing (TSP 2011), Budapest, Hungary, Aug. 18-20, 2011, pp. 469-471, 2011, IEEE, 978-1-4577-1410-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song |
Design and verification of an application-specific PLD using VHDL and SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 159-162, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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14 | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIFTS@FMCAD ![In: Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, Austin, USA, November 3, 2011, 2011, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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14 | Paramjot Saini, Mandeep Singh, Balwinder Singh |
VHDL Implementation of PCI Bus Arbiter Using Arbitration Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3 ![In: Contemporary Computing - 4th International Conference, IC3 2011, Noida, India, August 8-10, 2011. Proceedings, pp. 559-560, 2011, Springer, 978-3-642-22605-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Milind Khanapurkar, Jayant Y. Hande, Preeti R. Bajaj |
Approach for VHDL and FPGA Implementation of Communication Controller of FlexRay Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Hiding Multim. Signal Process. ![In: J. Inf. Hiding Multim. Signal Process. 1(4), pp. 325-336, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Francisco J. Azcondo, Angel de Castro, Christian Brañas |
Course on Digital Electronics Oriented to Describing Systems in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 57(10), pp. 3308-3316, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Isidoro Urriza, Luis Angel Barragan, Denis Navarro, José Ignacio Artigas, Oscar Lucía |
Word Length Selection Method for Controller Implementation on FPGAs Using the VHDL-2008 Fixed-Point and Floating-Point Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2010, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | David O'Sullivan, Donal Heffernan |
VHDL architecture for IEC 61499 function blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 4(6), pp. 515-524, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Akash Kumar Gupta, Sanjeet Kumar |
VHDL Implementation of different Turbo Encoder using Log-MAP Decoder ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1005.5361, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | M. Kamaraju, A. V. N. Tilak, K. Lal Kishore, K. Baburao |
VHDL Implementation and Verification of ARINC-429 Core ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1011.5374, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Oana Boncalo, Alexandru Amaricai, Mihai Udrescu, Mircea Vladutiu |
Quantum circuit's reliability assessment with VHDL-based simulated fault injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 50(2), pp. 304-311, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Roberto d'Amore |
A Synthesis-Oriented VHDL Course. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Educ. ![In: ACM Trans. Comput. Educ. 10(2), pp. 6:1-6:24, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Eladio Gutiérrez, María A. Trenas, Julián Ramos, Francisco Corbera, Sergio Romero 0001 |
A new Moodle module supporting automatic verification of VHDL-based assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Educ. ![In: Comput. Educ. 54(2), pp. 562-577, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Ali Hayek, Michael Schreiber, Josef Börcsök |
Basic VHDL tests conforming to IEC 61508. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INSS ![In: Seventh International Conference on Networked Sensing Systems, INSS 2010, Kassel, Germany, June 15-18, 2010, pp. 41-44, 2010, IEEE, 978-1-4244-7910-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Sergey Mikhtonyuk, Maksim Davydov, Roman Hwang, Dmitry Shcherbin |
IEEE 1500 compliant test wrapper generation tool for VHDL models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pp. 495-499, 2010, IEEE Computer Society, 978-1-4244-9555-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Manfred Dietrich, Uwe Eichler, Joachim Haase |
Digital statistical analysis using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 1007-1010, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Shaila Subbaraman, Manish M. Patil, Prashant S. Nilkund |
Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 11th International Conference on Control, Automation, Robotics and Vision, ICARCV 2010, Singapore, 7-10 December 2010, Proceedings, pp. 1791-1795, 2010, IEEE, 978-1-4244-7814-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Tolga Ayav, Tugkan Tuglular, Fevzi Belli |
Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSIRI (Companion) ![In: Fourth International Conference on Secure Software Integration and Reliability Improvement, SSIRI 2010, Singapore, June 9-11, 2010 - Companion Volume, pp. 46-53, 2010, IEEE Computer Society, 978-0-7695-4087-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Cédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, Slavisa Jovanovic |
Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010, pp. 135-139, 2010, KIT Scientific Publishing, 978-3-86644-515-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef |
Verification of a VHDL GPS baseband processor using a simulink-based test bench generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 327-330, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Nicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt, Ivan Grech |
VHDL implemetation of a DMX512 decoder on a FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 710-713, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Sahbi Baccar, Timothée Levi, Dominique Dallet, Vladimir Shitikov, François Barbara |
A behavioral and temperature measurements-based modeling of an operational amplifier using VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 343-346, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Stefan Potyra, Matthias Sand, Volkmar Sieh, Dietmar Fey |
Seamless high speed simulation of VHDL components in the context of comprehensive computing systems using the virtual machine faumachine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 2010 Winter Simulation Conference, WSC 2010, Baltimore, Maryland, USA, 5-8 December 2010, pp. 891-902, 2010, IEEE, 978-1-4244-9864-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Jimmy Xu, Nikhil Subramanian, Adam M. Alessio, Scott Hauck |
Impulse C vs. VHDL for Accelerating Tomographic Reconstruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010, pp. 171-174, 2010, IEEE Computer Society, 978-0-7695-4056-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Charles André, Frédéric Mallet, Julien DeAntoni |
VHDL Observers for Clock Constraint Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Fifth International Symposium on Industrial Embedded Systems, SIES 2010, University of Trento, Italy, July 7-9, 2010, pp. 98-107, 2010, IEEE, 978-1-4244-5840-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Stefan Hauser |
Entwurf eines generischen, applikationsspezifischen, transportgesteuerten Prozessor-Modells in VHDL und Validierung auf einem FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Informatiktage ![In: Informatiktage 2010 - Fachwissenschaftlicher Informatik-Kongress 19. und 20. März 2010, B-IT Bonn-Aachen International Center for Information Technology in Bonn, pp. 169-172, 2010, GI, 978-3-88579-443-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Marie Rouvière, Emmanuelle Bourdel, Sébastien Quintanel, Bertrand Granado |
VHDL-AMS model of RF-Interconnect System for Global On-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK, pp. 155-158, 2010, ECSI, Electronic Chips & Systems design Initiative. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault |
Formal Verification of Timed VHDL Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK, pp. 80-85, 2010, ECSI, Electronic Chips & Systems design Initiative. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Bharati B. Sayankar, P. H. Rangaree, S. D. Giripunje |
Filtering of Images by Kalman Filter Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: 3rd International Conference on Emerging Trends in Engineering and Technology, ICETET 2010, Goa, India, November 19-21, 2010, pp. 741-744, 2010, IEEE Computer Society, 978-0-7695-4246-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Prachi Rane |
Design of Modbus Controller Using VHDL for Remote Administrations of a Network of Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: 3rd International Conference on Emerging Trends in Engineering and Technology, ICETET 2010, Goa, India, November 19-21, 2010, pp. 694-697, 2010, IEEE Computer Society, 978-0-7695-4246-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Abdulhadi Shoufan |
A compact course on VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 89-92, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | Tomás G. Moreira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Jean-François Pétin, Eric Levrat |
Generating VHDL Source Code from UML Models of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIPES/BICC ![In: Distributed, Parallel and Biologically Inspired Systems - 7th IFIP TC 10 Working Conference, DIPES 2010 and 3rd IFIP TC 10 International Conference, BICC 2010, Held as Part of WCC 2010, Brisbane, Australia, September 20-23, 2010. Proceedings, pp. 125-136, 2010, Springer, 978-3-642-15233-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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14 | John M. Espinosa-Duran, Vladimir Trujillo-Olaya, Jaime Velasco-Medina, Raoul Velazco |
Bit-flip injection strategies for FSMs modeled in VHDL behavioral level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 11th Latin American Test Workshop, LATW 2010, Punta del Este, Uruguay, March 28-30, 2010, pp. 1-5, 2010, IEEE, 978-1-4244-7786-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Mary M. Randolph-Gips |
Metabolic Pathways Modeling using VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BICoB ![In: Proceedings of the ISCA 2nd International Conference on Bioinformatics and Computational Biology, BICoB-2010, March 24-26, 2010, Sheraton Waikiki Hotel, Honolulu, Hawaii, USA, pp. 50-54, 2010, ISCA, 978-1-880843-76-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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14 | Julian A. Bailey |
Towards the neurocomputer : an investigation of VHDL neuron models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2010 |
RDF |
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14 | Leran Wang, Tom J. Kazmierski |
VHDL-AMS Based Genetic Optimization of Mixed-Physical-Domain Systems in Automotive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. ![In: Simul. 85(10), pp. 661-670, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Christopher Pohl, Carlos Paiz, Mario Porrmann |
vMAGIC - Automatic Code Generation for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2009, pp. 205149:1-205149:9, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Takialddin Al-smadi |
Learning to Computer Architecture Courses Using Verilog Hardware Description Language (VHDL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Egypt. Comput. Sci. J. ![In: Egypt. Comput. Sci. J. 31(3), 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
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14 | Silvano R. Rossi, Edward David Moreno, Aparecido Augusto de Carvalho, Alexandre C. R. da Silva, Edson Antonio Batista, Thiago Alexandre Prado, Tércio A. Santos Filho |
A VHDL-based protocol controller for NCAP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Stand. Interfaces ![In: Comput. Stand. Interfaces 31(2), pp. 515-522, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Martin Schubert |
An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(12), pp. 2717-2727, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Roberto Sepúlveda, Oscar Montiel, José Angel Olivas, Oscar Castillo 0001 |
Methodology to Test and Validate a VHDL Inference Engine of a Type-2 FIS, through the Xilinx System Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control ![In: Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control, pp. 295-308, 2009, Springer, 978-3-642-04513-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Rohit Sharma, Vivek Kumar Sehgal, Nitin 0001, Pranav Bhasker, Ishita Verma |
Design and Implementation of a 64-bit RISC Processor Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UKSim ![In: Proceedings of the UKSim'11, International Conference on Computer Modelling and Simulation, Cambridge University, Emmanuel College, Cambridge, UK, 25-27 March 2009, pp. 568-573, 2009, IEEE Computer Society, 978-0-7695-3593-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Lixin Cheng, Jinian Bian, Yunyun Liu |
An approach to synthesis delay semantics in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAD/Graphics ![In: 11th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2009, Huangshan, China, August 19-21, 2009, pp. 492-496, 2009, IEEE, 978-1-4244-3699-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Shadi Moazzeni, Saadat Poormozaffari, Amin Emami |
An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009, pp. 55-60, 2009, IEEE Computer Society, 978-0-7695-4000-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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14 | Sven Slawinski, Lutz Zacharias, Robert Dorn, Johann Hauer |
Erstellung und Verifizierung eines VHDL-AMS-Modells für einen kapazitiven Delta-Sigma-Modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, pp. 227-236, 2009, Universitätsbibliothek Berlin, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
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