Search results for "VLSI-DAT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu	Ultrasonic telemetry and neural stimulator with FSK-PWM signaling.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang	A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang	Thermal coupling aware task migration using neighboring core search for many-core systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa	An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chun-Yi Yeh, Hung-Chih Chiu, Hsi-Pin Ma	An information hub for implantable wireless brain machine interface.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu	Case study of yield learning through in-house flow of volume diagnosis.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Chin Yin, Chih-Cheng Hsieh	A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Sanjeev Jain, Sheng-Lyang Jang, Miin-Horng Juang	A 4.0/7.5-GHz dual-band LC VCO in 0.18-μm SiGe BiCMOS technology.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	John Goodacre	ARM next generation 64bit processors for power efficient compute.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Ding-Yun Chen, Chi-Cheng Ju, Chen-Tsai Ho, Chung-Hung Tsai	MVSE: A Multi-core Video decoder System level analytics Engine.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Hang Lv 0002, Bo Zhou 0008, Dang Liu, Woogeun Rhee, Yongming Li 0004, Zhihua Wang 0001	A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar	What happens when circuits grow old: Aging issues in CMOS design.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Erik Jan Marinissen	Creating options for 3D-SIC testing.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay	A Cycle Count Accurate TLM bus modeling approach.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Jheng-Hao Ye, Tsung-Wei Hung, Ming-Der Shieh	Energy-efficient architecture for word-based Montgomery modular multiplication algorithm.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang	An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
1	Yuan-Chuan Steven Chen, Dave Budka, Auston Gibertini, Dan Bockelman, Yutien Lin	Design validation on multiple-core CPU supported low power states using platform based infrared emission microscopy (PIREM) technique.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chih-Ting Yeh, Ming-Dou Ker	New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu	Test for more than pass/fail using on-chip temperature sensor.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Hui Geng, Yiyu Shi 0001, Ming Dong, Runsheng Liu	A master-slave SoC structure for HMM based speech recognition.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	An-Yeu Wu, Li-C. Wang	Foreword.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Xi-Rui Wang, Hsi-Pin Ma, Jen-Yuan Hsu, Pangan Ting	Large set construction of user uplink ranging codes for M2M applications.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Gary Huang	Powerful smartphone solutions unleashing new technology innovations.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Kevin Ho, Tsung-Yi Chou, Po-Kai Chen, David J. Liou	High speed DDR2/3 PHY and dual CPU core design for 28nm SoC.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Michel Brillouët, Shyh-Jye Jou, C. Patrick Yue	Welcome from the general chairs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Sheng-Jhih Jiang, Chan-Liang Wu, Tsung-Yi Ho	A nonlinear optimization methodology for resistor matching in analog integrated circuits.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	David Z. Pan, Jhih-Rong Gao, Bei Yu 0001	VLSI CAD for emerging nanolithography.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Wei-Ning Liu, Tsung-Hsien Lin	An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filter.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda	A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Guixuan Liang, Danping He, Jorge Portilla, Teresa Riesgo	A hardware in the loop design methodology for FPGA system and its application to complex functions.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Xiongxin Zhao, Zhixiang Chen 0002, Xiao Peng 0002, Dajiang Zhou, Satoshi Goto	DVB-T2 LDPC decoder with perfect conflict resolution.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	B.-Y. Jan, J.-L. Huang	A fault-tolerant PE array based matrix multiplier design.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Xuefeng Zhu, Huawei Li 0001, Xiaowei Li 0001	Statistical SDFC: A metric for evaluating test quality of small delay faults.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Peter Lemmens	Disruptive technologies for the future generation smart systems.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Cheng-Ta Wu, Feng-Xiang Huang, Kuan-Fu Kuo, Ing-Jer Huang	An OCP-AHB bus wrapper with built-in ICE support for SOC integration.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Doug Kwan, Jing Yu, Bhaskar Janakiraman	Google's C/C++ toolchain for smart handheld devices.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Leo Lorenz	Power semiconductor-driving technology for high power green electronic systems.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Liang-Chi Chiu, Tian-Sheuan Chang	A lossless embedded compression codec engine for HD video decoding.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang	A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee	A low cost DPA-resistant 8-bit AES core based on ring oscillators.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Hidemi Takasu	Silicon Carbide devices open a new era of power electronics.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Jia-Nan Tai, Hsin-Shu Chen, Hang-Quei Chiu	A highly integrated class-D amplifier using driver delay hysteresis control.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yin-Tsung Hwang, Sung-Jun Tsai, Yi-Yo Chen	Design and implementation of an optical OFDM baseband receiver in FPGA.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Cihun-Siyong Alex Gong, Kai-Wen Yao, Jyun-Yue Hong, Muh-Tian Shiue	On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystem.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng	Challenges and solutions in modern analog placement.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yung-Kuei Lu, Ming-Der Shieh	Efficient architecture for Reed-Solomon decoder.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Lin Lin, Weber Chien	Emerging touch techniques in smart handheld device.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu	A fast-locking phase-locked loop using CP control and gated VCO.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chi-Cheng Ju, Yung-Chang Chang, Chih-Ming Wang, Chun-Chia Chen, Hue-Min Lin, Chia-Yun Cheng, Fred Chiu, Sheng-Jen Wang, Tsu-Ming Liu, Chung-Hung Tsai	A 363-µW/fps power-aware green multimedia processor for mobile applications.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Ruili Wu, Yan Li 0008, Jerry Lopez, Donald Y. C. Lie	A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiency.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Chin-Fu Lin	A 1-V, 44.6 ppm/°C bandgap reference with CDS technique.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	Computer architecture for die stacking.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty	3D IC test scheduling using simulated annealing.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Kun-Chih Chen, Chih-Hao Chao, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Wu	Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Brian Lee	Review of 3D high density storage class memory (SCM) architecture.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Jen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, Po-Chiun Huang	A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto	A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Roberto Bez, Paolo Cappelletti	Emerging memory technology perspective.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chia-Chi Ho, Tai-Cheng Lee	A 10-bit 200-MS/s reconfigurable pipelined A/D converter.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yi-Jun Liu, Chih-Chyau Yang, Shih-Lun Chen, Chun-Chieh Chiu, Chien-Ming Wu, Chun-Ming Huang	An efficient memory controller for 3D heterogeneous integration platform.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Zheng Wang 0020, Xiao Wang, Anupam Chattopadhyay, Zoltan Endre Rakosi	ASIC synthesis using Architecture Description Language.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Kevin J. Nowka	Transforming memory systems: Optimizing for client value on emerging workloads.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chun-Lin Ko, Chieh-Pin Chang, Chien-Nan Kuo, Da-Chiang Chang, Ying-Zong Juang	A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Guan-Ru Li, Bo-Cheng Charles Lai	A highly parallel design of image surface layout recovering on GPGPU.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chih-Kai Yang, Chi-Hsuan Hsieh, Yuan-Hao Huang	An energy-saving spectrum sensing processor based on partial discrete wavelet packet transform.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Nasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd	Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu	Peak wake-up current estimation at gate-level with standard library information.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	K. Lawrence Loh	Technology and design challenges for smartphone SOCs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chien-Hui Liao, Hung-Pin Wen	Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih	An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou	3-D centric technology and realization with TSV.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Ching-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu	Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Nik Sumikawa, Wen Chen 0016, Li-C. Wang	Data mining based prediction paradigm and its applications in design automation.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Simon Jiang, Frankwell Lin	The best SoC solution with AndesCore and Andes's platform.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Xin-Tian Wu, Kai-Hua Hsu, Lynn C.-L. Chang, Charles H.-P. Wen	Spatial-correlation-aware soft error rate analysis using quasi-importance sampling.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Tzon-Tzer Lu, Hua-Chin Lee, Chao-Shiun Wang, Chorng-Kuang Wang	A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Jyun-Cheng Wu, Lei Chen, Tzi-Dar Chiueh	Design of a real-time software-based GPS baseband receiver using GPU acceleration.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Fu-Chen Chen, Yung-Lin Huang, Shao-Yi Chien	Hardware-efficient true motion estimator based on Markov Random Field motion vector correction.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Chu-Jung Sha, Chun-Lin Ko, Da-Chiang Chang, Ying-Zong Juang	Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng, Jiun-In Guo	A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Rongxiang Wu, Salahuddin Raju, Mansun Chan, Johnny K. O. Sin, C. Patrick Yue	Wireless power link design using silicon-embedded inductors for brain-machine interface.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Tim Whitfield	The 2012 ARM powered compute subsystem - delivering the smart handheld platform.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Cong Hao, Song Chen 0001, Takeshi Yoshimura	Port assignment for interconnect reduction in high-level synthesis.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Ya-Qin Zhang	Advances in computing.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng	Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Sheng-Wei Fan, Jia-Wai Chen, Jiun-In Guo	Low bandwidth HD1080@60FPS JPEG-XR transform design.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Tao Jiang 0005, Kangmin Hu, Patrick Yin Chiang	A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1		Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012	VLSI-DAT	2012	DBLP BibTeX RDF
1	Philippe Magarshack, Andreia Cathelin	Gaining 10x in energy efficiency in the next decade in consumer products.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li 0001	Area and reliability efficient ECC scheme for 3D RAMs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yun-Yen ChenWu, Hsi-Pin Ma, Chaitali Biswas, Dejan Markovic	Universal architecture prototype for patient-centric medical environment.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang	A slew rate self-adjusting 2×VDD output buffer With PVT compensation.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yu-Jen Huang, Jin-Fu Li 0001, Che-Wei Chou	Post-bond test techniques for TSVs with crosstalk faults in 3D ICs.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang	A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Shih-Nung Wei, Yi-Ming Wang, Jyun-Hua Peng, Yuandi Surya	A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuit.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	WeiXiang Tang, Yursun Hsu	Design of a pipelined clos network with late release scheme.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Ambient electronics and ultra-low power LSI design.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Po-Hsiang Lan, Yao-Jun Kuo, Po-Chiun Huang	An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Shin-Jye Hsu, Che-Yu Lu, Chung-Chih Hung	40MHz Gm-C filter with high linearity OTA for wireless applications.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
1	Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee	Routing-efficient implementation of an internal-response-based BIST architecture.	VLSI-DAT	2012	DBLP DOI BibTeX RDF

Publications at "VLSI-DAT"( http://dblp.L3S.de/Venues/VLSI-DAT )