Search results for "clocking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
10	Suhwan Kim, Marios C. Papaefthymiou	True single-phase adiabatic circuitry.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
10	Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung	Low-power high-level synthesis using latches.	ASP-DAC	2001	DBLP DOI BibTeX RDF
10	Jose Luis Nunez, Claudia Feregrino, Simon R. Jones, Stephen Bateman	X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor.	FPL	2001	DBLP DOI BibTeX RDF
10	Alvin R. Albrecht, Alan J. Hu	Register Transformations with Multiple Clock Domains.	CHARME	2001	DBLP DOI BibTeX RDF
10	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Qing K. Zhu, Michael Zhang	Low-voltage swing clock distribution schemes.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Alex R. Bugeja, Sung-Ung Kwak	Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen	Power modeling and low-power design of content addressable memories.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Burkart Voss, Manfred Glesner	A low power sinusoidal clock.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Haining Wang, Kang G. Shin	Robust TCP Congestion Recovery.	ICDCS	2001	DBLP DOI BibTeX RDF
10	Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura	Scaling Up Of Wave Pipelines.	VLSI Design	2001	DBLP DOI BibTeX RDF
10	Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser	Threshold logic circuit design of parallel adders using resonant tunneling devices.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Johnny Pihl	Design automation with the TSPC circuit technique: a high-performance wave digital filter.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Leonie Ruth Simpson, Ed Dawson, Jovan Dj. Golic, William Millan	LILI Keystream Generator.	Selected Areas in Cryptography	2000	DBLP DOI BibTeX RDF
10	Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni	A 50 Mbit/s Iterative Turbo-Decoder.	DATE	2000	DBLP DOI BibTeX RDF
10	George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001	An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.	ASYNC	2000	DBLP DOI BibTeX RDF
10	John S. McCaskill, Robert Penchovsky, Marlies Gohlke, Jörg Ackermann, Thomas Rücker	Steady Flow Micro-Reactor Module for Pipelined DNA Computations.	DNA Computing	2000	DBLP DOI BibTeX RDF
10	Alex Biryukov, Adi Shamir, David A. Wagner 0001	Real Time Cryptanalysis of A5/1 on a PC.	FSE	2000	DBLP DOI BibTeX RDF
10	Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson 0001	Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.	ICCD	2000	DBLP DOI BibTeX RDF
10	Vivek Chickermane, Scott Richter, Carl Barnhart	Integrating Logic BIST in VLSI Designs with Embedded Memories.	VTS	2000	DBLP DOI BibTeX RDF
10	M. Srikanth Rao, S. K. Nandy 0001	Power minimization using control generated clocks.	DAC	2000	DBLP DOI BibTeX RDF
10	Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems	The spring scheduling coprocessor: a scheduling accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
10	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Guido Arnout	C for System Level Design.	DATE	1999	DBLP DOI BibTeX RDF
10	Xinghao Chen 0004, Thomas J. Snethen, Joe Swenton, Ron Walther	A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, DFT
10	Doug Malone	Design Validation of .18 um 1 Ghz Cache and Register Arrays.	MTDT	1999	DBLP DOI BibTeX RDF
10	Min Zhao 0001, Sachin S. Sapatnekar	Timing-driven partitioning for two-phase domino and mixed static/domino implementations.	ICCAD	1999	DBLP DOI BibTeX RDF
10	Pietro Andreani, Lars Sundström, Niklas Karlsson, M. Svensson	A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Fenghao Mu, Christer Svensson	High speed interface for system-on-chip design by self-tested self-synchronization.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	M. B. Maaz, Magdy A. Bayoumi	A non-zero clock skew scheduling algorithm for high speed clock distribution network.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
10	Jae J. Chang, Myunghee Lee, Sungyong Jung, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills	Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
10	Renato Menicocci, Jovan Dj. Golic	Edit Probability Correlation Attack on the Bilateral Stop/Go Generator.	IMACC	1999	DBLP DOI BibTeX RDF	mutual clock control, bilateral stop/go, edit probability, Stream ciphers, correlation attack
10	Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman	Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
10	Josef Schmid, Joachim Knäblein	Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.	VTS	1999	DBLP DOI BibTeX RDF
10	Bupesh Pandita, Subir K. Roy	Design and Implementation of Viterbi Decoder Using FPGAs.	VLSI Design	1999	DBLP DOI BibTeX RDF
10	Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar	A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.	VLSI Design	1999	DBLP DOI BibTeX RDF
10	Dave Johnson 0003, Venkatesh Akella, Bret Stott	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
10	Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen	Efficient timing analysis for CMOS circuits considering data dependent delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Feng Zhou, Peter Kornerup	A New Fast Discrete Fourier Transform.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
10	Suhwan Kim, Marios C. Papaefthymiou	True single-phase energy-recovering logic for low-power, high-speed VLSI.	ISLPED	1998	DBLP DOI BibTeX RDF
10	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
10	E. Kofi Vida-Torku, George Joos	Designing for scan test of high performance embedded memories.	ITC	1998	DBLP DOI BibTeX RDF
10	Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal	Logic emulation with virtual wires.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
10	Kris Gaj, Eby G. Friedman, Marc J. Feldman	Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
10	Andre Hertwig, Hans-Joachim Wunderlich	Fast controllers for data dominated applications.	ED&TC	1997	DBLP DOI BibTeX RDF
10	Jovan Dj. Golic	Cryptanalysis of Alleged A5 Stream Cipher.	EUROCRYPT	1997	DBLP DOI BibTeX RDF
10	Kevin J. Nowka, H. Peter Hofstee	Circuits and Microarchitecture for Gigahertz VLSI Designs.	ARVLSI	1997	DBLP DOI BibTeX RDF
10	Jovan Dj. Golic, Renato Menicocci	Edit Distance Correlation Attack on the Alternating Step Generator.	CRYPTO	1997	DBLP DOI BibTeX RDF	clock-controlled shift registers, alternating step generator, cryptanalysis, Stream ciphers, edit distance, correlation attacks
10	Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska	Clock skew optimization for ground bounce control.	ICCAD	1996	DBLP DOI BibTeX RDF
10	Priyadarsan Patra, Donald S. Fussell	Efficient Delay-Insensitive RSFQ Circuits.	ICCD	1996	DBLP DOI BibTeX RDF
10	Ahmed El-Amawy, Priyalal Kulasinghe	Properties of Generalized Branch and Combine Clock Networks.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
10	Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj	Timing and area optimization for standard-cell VLSI circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach	The SNAP Project: Towards Sub-Nanosecond Arithmetic.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating-point multiplication, computer arithmetic, floating-point arithmetic, wave pipelining, floating-point addition
10	K. J. Singh, P. A. Subrahmanyam	Extracting RTL models from transistor netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	Switch-level simulation, Formal verification, Extraction, RTL model
10	Jovan Dj. Golic	Towards Fast Correlation Attacks on Irregularly Clocked Shift Registers.	EUROCRYPT	1995	DBLP DOI BibTeX RDF
10	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
10	Li-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du	The calculation of signal stable ranges in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
10	C. Thomas Gray, Wentai Liu, Ralph K. Cavin III	Timing constraints for wave-pipelined systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
10	Sonya Gary, Pete Ippolito, Gianfranco Gerosa, Carl Dietz, Jim Eno, Hector Sanchez	PowerPC 603, A Microprocessor for Portable Computers.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
10	Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Teresa H.-Y. Meng, Robert W. Brodersen, David G. Messerschmitt	Automatic synthesis of asynchronous circuits from high-level specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
10	Miriam Leeser	Reasoning about the function and timing of integrated circuits with interval temporal logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
10	Nohbyung Park, Alice C. Parker	Sehwa: a software package for synthesis of pipelines from behavioral specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
10	Craig Hansen	Hardware Logic Simulation by Compilation.	DAC	1988	DBLP BibTeX RDF
10	Kye S. Hedlund	Aesop: A Tool for Automated Transistor Sizing.	DAC	1987	DBLP DOI BibTeX RDF
10	Larry G. Jones, Janos Simon	Hierarchical VLSI Design Systems Based on Attribute Grammars.	POPL	1986	DBLP DOI BibTeX RDF
10	Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man	An intelligent module generator environment.	DAC	1986	DBLP DOI BibTeX RDF
10	Nohbyung Park, Alice C. Parker	Sehwa: a program for synthesis of pipelines.	DAC	1986	DBLP DOI BibTeX RDF
10	Wayne H. Wolf	An object-oriented, procedural database for VLSI chip planning.	DAC	1986	DBLP DOI BibTeX RDF
10	Bernhard Smeets	A Note On Sequences Generated by Clock Controlled Shift Registers.	EUROCRYPT	1985	DBLP DOI BibTeX RDF