Search results for "reconfigurability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Stephen Charlwood, Philip James-Roxby	Evaluation of the XC6200-series Architecture for Cryptographic Applications.	FPL	1998	DBLP DOI BibTeX RDF
10	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik	Solving Boolean Satisfiability with Dynamic Hardware Configurations.	FPL	1998	DBLP DOI BibTeX RDF
10	Jeffrey W. Amos	Emerging Partnership Strategy at Sandia National Laboratories.	HICSS (6)	1998	DBLP DOI BibTeX RDF
10	Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta	Hardware/Software Co-design of a High-end Mixed Signal Microcontroller.	VLSI Design	1998	DBLP DOI BibTeX RDF	Mixed sigal microcontroller, Signal Processing, Hardware/Software Co-design
10	Suchendra M. Bhandarkar, Hamid R. Arabnia	Parallel Computer Vision on a Reconfigurable Multiprocessor Network.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Reconfigurable multiring network, computer vision, parallel algorithms, image processing, parallel processing, distributed algorithms, distributed processing, reconfigurable architectures, scalable architectures
10	Ju-wook Jang, Madhusudan Nigam, Viktor K. Prasanna, Sartaj Sahni	Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF
10	Laurent Moll, Mark Shand	Systems performance measurement on PCI Pamette.	FCCM	1997	DBLP DOI BibTeX RDF
10	Baback A. Izadi, Füsun Özgüner	Design of a Circuit-Switched Highly Fault-Tolerant k-ary n-cube.	ICPP	1997	DBLP DOI BibTeX RDF	augmented multiprocessor, spare allocation, Fault tolerance, reconfiguration, k-ary n-cube
10	Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar	A Novel Reconfigurable Co-Processor Architecture.	VLSI Design	1997	DBLP DOI BibTeX RDF
10	Hermann de Meer, Hana Sevcikova	PENELOPE: Dependability Evaluation and the Optimization of Performability.	Computer Performance Evaluation	1997	DBLP DOI BibTeX RDF
10	James B. Peterson, Peter M. Athanas	High-speed 2-D convolution with a custom computing machine.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
10	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
10	Alfred Strey, Narcís Avellana, Raul Holgado, J. Alberto Fernández, Ramon Capillas, Elena Valderrama	A Massively Parallel Neurocomputer with a Reconfigurable Arithmetical Unit.	IWANN	1995	DBLP DOI BibTeX RDF
10	Mark Shand	Flexible image acquisition using reconfigurable hardware.	FCCM	1995	DBLP DOI BibTeX RDF
10	Alfred Strey, Narcís Avellana, Raul Holgado, Ramon Capillas, J. Alberto Fernández, Elena Valderrama	A Configurable Parallel Neurocomputer.	ANNES	1995	DBLP DOI BibTeX RDF	neural hardware, parallel computer, neurocomputer
10	Lizyamma Kurian, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
10	Vipul Gupta, Eugen Schenfeld	Performance analysis of a synchronous, circuit-switched interconnection cached network.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
10	Marcello Chiaberge, Dante Del Corso, Francesco Gregoretti, Leonardo Maria Reyneri	A Neural Network Chip Using CPWM Modulation.	IWANN	1993	DBLP DOI BibTeX RDF
10	Mark Shand, Jean Vuillemin	Fast implementations of RSA cryptography.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
10	Jung Hwan Kim, Phill-Kyu Rhee	A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
10	Gul Agha	The Structure and Semantics of Actor Languages.	REX Workshop	1990	DBLP DOI BibTeX RDF	Programming Language Theory, Concurrent Programming Structures, Distributed Systems, Concurrency, Object-Oriented Programming, Actors, Multiprocessor Architectures
10	Chungti Liang, Wei-Tek Tsai	Multi-failure fault-tolerance of embedded loops on hypercubes: issues and performance study.	SPDP	1990	DBLP DOI BibTeX RDF
10	Richard E. Schantz, Ken Schroder, Paul Neves	Resource management in the Cronus distributed operating system.	Comput. Commun. Rev.	1987	DBLP DOI BibTeX RDF
10	Gul Agha, Carl Hewitt	Concurrent Programming Using Actors: Exploiting large-Scale Parallelism.	FSTTCS	1985	DBLP DOI BibTeX RDF
10	Kemal Oflazer	A reconfigurable VLSI architecture for a database processor.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF