| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Stephan Bourduas, Zeljko Zilic |
Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing.  |
ASAP  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sherman Braganza, Miriam Leeser |
The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumit D. Mediratta, Jeffrey T. Draper |
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Walid Ibrahim, Valeriu Beiu |
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Zhou 0018, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu |
Hardware Acceleration for 3-D Radiation Dose Calculation. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Doran K. Wilde |
Computing Digit Selection Regions for Digit Recurrences. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Christophe Wolinski, Krzysztof Kuchcinski |
Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | D. A. Armstrong, M. W. Pearson |
A Rapid Prototyping Platform for Wireless Medium Access Control Protocols. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jie Guo 0007, Jun Liu, Björn Mennenga, Gerhard P. Fettweis |
A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis |
SIMD Vectorization of Histogram Functions. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | David Montgomery, Ali Akoglu |
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007 |
ASAP |
2007 |
DBLP BibTeX RDF |
|
| 1 | Maria G. Koziri, Antonios N. Dadaliaris, Georgios I. Stamoulis, Ioannis Katsavounidis |
A Novel Low-Power Motion Estimation Design for H.264. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel |
A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Pramod Kumar Meher |
Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m). |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | William Josephson, Ruby B. Lee, Kai Li 0001 |
ISA Support for Fingerprinting and Erasure Codes. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Dou, Jie Zhou 0007, Yuanwu Lei, Xingming Zhou |
FPGA SAR Processor with Window Memory Accesses. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Tsen, Michael J. Schulte, Sonia González-Navarro |
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Caroline Collange, Marc Daumas, David Defour |
Graphic processors to speed-up simulations for the design of high performance solar receptors. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixing Ji, Feng Shi 0009, Baojun Qiao, Muhammad Kamran |
The Design of a Novel Object-oriented Processor : OOMIPS. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Shi 0009, Weixing Ji, Baojun Qiao, Bin Liu, Haroon-ul-Rashid |
A Triplet-based Computer Architecture Supporting Parallel Object Computing. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ben Cope, Peter Y. K. Cheung, Wayne Luk |
Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll |
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold |
LNS Subtraction Using Novel Cotransformation and/or Interpolation. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith |
An Application Specific Memory Characterization Technique for Co-processor Accelerators. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
A Self-Reconfigurable Implementation of the JPEG Encoder. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcel Bimberg, Marcos B. S. Tavares, Emil Matús, Gerhard P. Fettweis |
A High-Throughput Programmable Decoder for LDPC Convolutional Codes. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jahyun J. Koo, David Fernández, Ashraf Haddad, Warren J. Gross |
Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandra Aguiar, Márcio Eduardo Kreutz, Rafael Santos, Tatiana Santos |
Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hau T. Ngo, Satyanadh Gundimada, Vijayan K. Asari |
Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video Stream. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, Xiexiong Chen |
An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Filipa Duarte, Stephan Wong |
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Nibbelink, Sanjay V. Rajopadhye, Richard McConnell |
0/1 Knapsack on Hardware: A Complete Solution. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Huang 0001, D. Grunert, Lothar Thiele |
Windowed FIFOs for FPGA-based Multiprocessor Systems. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | C. Boustany, Ahmed Lakhsasi, Mohammed Bougataya |
Design and implementation of a surface peak thermal detector algorithm. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alp Arslan Bayrakci, Ahmet Akkas |
Reduced Delay BCD Adder. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | David B. Thomas, Jacob A. Bower, Wayne Luk |
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alain Darte, C. Quinson |
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois |
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Abdullah Al Faruque, Jörg Henkel |
Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Milos D. Ercegovac, Jean-Michel Muller |
A Hardware-Oriented Method for Evaluating Complex Polynomials. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric M. Schwarz, Steven R. Carlough |
Power6 Decimal Divide. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Kikkeri, Peter-Michael Seidel |
An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan |
Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Bonzini, Laura Pozzi |
A Retargetable Framework for Automated Discovery of Custom Instructions. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner |
Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Julio Villalba, Javier Hormigo, Tomás Lang |
Improving the Throughput of On-line Addition for Data Streams. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Roberto R. Osorio, Javier D. Bruguera |
Entropy Coding on a Programmable Processor Array for Multimedia SoC. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhixiong Zhou, Hu He 0001, Yanjun Zhang, Yihe Sun, Adriel Cheng |
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola |
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahzad Azarmehr, Roberto Muscedere |
A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Siew Kei Lam, Thambipillai Srikanthan |
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Haibo Zhu, Partha Pratim Pande, Cristian Grecu |
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismo Hänninen, Jarmo Takala |
Robust Adders Based on Quantum-Dot Cellular Automata. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Pablo Ituero, Marisa López-Vallejo |
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | |
Program Committee. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger |
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede |
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas B. Preußer, Rainer G. Spallek |
Analysis of a Fully-Scalable Digital Fractional Clock Divider. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | John V. McCanny, Roger F. Woods, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Florin Balasa, Per Gunnar Kjeldsberg, Martin Palkovic, Arnout Vandecappelle, Francky Catthoor |
Loop Transformation Methodologies for Array-Oriented Memory Management. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aydin O. Balkan, Gang Qu 0001, Uzi Vishkin |
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Feng Xian, Witawas Srisa-an, Hong Jiang 0001 |
Evaluating Hardware Support for Reference Counting Using Software Configurable Processors. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kung Yao, Flavio Lorenzelli |
An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal Processing. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Guido Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni 0001 |
Speeding Up AES By Extending a 32 bit Processor Instruction Set. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Systolic FFT Processors: Past, Present and Future. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro |
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Tang, Tejas M. Bhatt, Vishwas Sundaramurthy |
Reconfigurable Shuffle Network Design in LDPC Decoders. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Neil Smyth, Máire McLoone, John V. McCanny |
An Adaptable And Scalable Asymmetric Cryptographic Processor. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | |
Message from the Conference Chairs. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel P. Lopresti |
Three Computationally Demanding Problems in Search of ASAP Solutions. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha |
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan He, Guan Qin, Mi Lu, Wei Zhao 0001 |
An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ed F. Deprettere, Todor P. Stefanov, Shuvra S. Bhattacharyya, Mainak Sen |
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata |
Pipelined Range Reduction for Floating Point Numbers. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Graham A. Jullien |
Array Processing Using Alternate Arithmetic - A 20 Year Legacy. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Brent E. Nelson |
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | DaeGon Kim, Sanjay V. Rajopadhye |
An Improved Systolic Architecture for LU Decomposition. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tung N. Pham, Earl E. Swartzlander Jr. |
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Elie H. Sarraf, Messaoud Ahmed Ouameur, Daniel Massicotte |
FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Youtao Zhang, Jun Yang 0002, Lan Gao |
Efficient Group KeyManagement with Tamper-resistant ISA Extensions. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Júlio C. B. de Mattos, Stephan Wong, Luigi Carro |
The Molen FemtoJava Engine. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan D. Castellanos, James E. Stine |
A 64-bit Decimal Floating-Point Comparator. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaoxiong Hua, Pushkin R. Pari, Gang Qu 0001 |
Dual-Processor Design of Energy Efficient Fault-Tolerant System. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey M. Arnold |
Software Configurable Processors. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede |
High Speed Channel Coding Architectures for the Uncoordinated OR Channel. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aasavari Bhave, Eurípides Montagne, Edgar Granados |
Describing Quantum Circuits with Systolic Arrays. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho |
Buffer and register allocation for memory space optimization. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson |
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | |
External Referees. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Richard Hughey, Andrea Di Blas |
The UCSC Kestrel Application-Unspecific Processor. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep B. Singh, Jayanta Biswas, S. K. Nandy 0001 |
A Cost Effective Pipelined Divider for Double Precision Floating Point Number. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula |
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Philippe Clauss, Bénédicte Kenmei |
Polyhedral Modeling and Analysis of Memory Access Profiles. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos |
An Energy-Delay Efficient Subword Permutation Unit. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo |
2D-VLIW: An Architecture Based on the Geometry of Computation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten |
Dynamic-SIMD for lens distortion compensation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina |
Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Siegel, Renate Merker |
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
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