Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Srinidhi Kestur, Mi Sun Park, Jagdish Sabarad, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla	Emulating Mammalian Vision on Reconfigurable Hardware.	FCCM	2012	DBLP DOI BibTeX RDF
1	Waheed Ahmed, Muhammad Shafique 0001, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker 0001	Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.	FCCM	2011	DBLP DOI BibTeX RDF
1	Peter Lieber, Brad L. Hutchings	FPGA Communication Framework.	FCCM	2011	DBLP DOI BibTeX RDF
1	Ming Yan 0003, Ziyu Yang, Sikun Li, Liu Yang	Reconsideration of Computing Paradigms and a Novel Reconfigurable Architecture.	FCCM	2011	DBLP DOI BibTeX RDF
1	Zain-ul-Abdin, Anders Ahlander, Bertil Svensson	Programming Real-Time Autofocus on a Massively Parallel Reconfigurable Architecture Using Occam-pi.	FCCM	2011	DBLP DOI BibTeX RDF
1	Paul Chow, Michael J. Wirthlin (eds.)	IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011	FCCM	2011	DBLP BibTeX RDF
1	Jian Li 0004, Marinko Sarunic, Lesley Shannon	Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Kostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos	Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors.	FCCM	2011	DBLP DOI BibTeX RDF
1	Liu Ling, Jincan Zhuang, Qianying Zhu, Shunyu Zhu, Zhiyuan Zhang, Xinxin Zhang, Lu Cao, Zhihong Yu, Xiangbin Wu, Dong Liu	An FPGA-Based Optical IOH Architecture for Embedded System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Aws Ismail, Lesley Shannon	FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators.	FCCM	2011	DBLP DOI BibTeX RDF
1	Bharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad	High-Throughput, Lossless Data Compresion on FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Yi-Hua Edward Yang, Oguzhan Erdem, Viktor K. Prasanna	High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search.	FCCM	2011	DBLP DOI BibTeX RDF
1	Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong	A Model for Peak Matrix Performance on FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Zhong-Ho Chen, Alvin Wen-Yu Su, Ming-Ting Sun, Scott Hauck	Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis Tool.	FCCM	2011	DBLP DOI BibTeX RDF
1	Emilio Castillo, Javier Castillo, Javier Cano 0001, Pablo Huerta, José Ignacio Martínez	A Key Size Configurable High Speed RSA Coprocessor.	FCCM	2011	DBLP DOI BibTeX RDF
1	Krishna K. Nagar, Jason D. Bakos	A Sparse Matrix Personality for the Convey HC-1.	FCCM	2011	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Simon A. Berger, Alexandros Stamatakis	Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Rohit Sinha 0001, Hiren D. Patel	Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis.	FCCM	2011	DBLP DOI BibTeX RDF
1	Matt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt	Efficient Calculation of Pairwise Nonbonded Forces.	FCCM	2011	DBLP DOI BibTeX RDF
1	Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French	The PowerPC 405 Memory Sentinel and Injection System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Matina Lakka, Grigorios Chrysos 0001, Ioannis Papaefstathiou, Apostolos Dollas	Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU.	FCCM	2011	DBLP DOI BibTeX RDF
1	Will X. Y. Li, Ray C. C. Cheung, Wei Zhang 0044, Rosa H. M. Chan, Dong Song, Theodore W. Berger	FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities.	FCCM	2011	DBLP DOI BibTeX RDF
1	Sebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001, Marco D. Santambrogio	Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Zheng Ding, Feng Zhao, Tinghui Wang, Wei Shu, Min-You Wu	Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board.	FCCM	2011	DBLP DOI BibTeX RDF
1	Davor Capalija, Tarek S. Abdelrahman	Towards Synthesis-Free JIT Compilation to Commodity FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan	An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.	FCCM	2011	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, Bin Huang, Ron Sass, Matthew French	Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Yun Liang 0001, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong	Multilevel Granularity Parallelism Synthesis on FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Suraj Gowda, Aaron Parsons, Robert Jarnot, Dan Werthimer	Automated Placement for Parallelized FPGA FFTs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Sascha Mühlbach, Andreas Koch 0001	A Scalable Multi-FPGA Platform for Complex Networking Applications.	FCCM	2011	DBLP DOI BibTeX RDF
1	Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis, Konstantinos Krommydas, G. Tsoumblekas	Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore Processors.	FCCM	2011	DBLP DOI BibTeX RDF
1	Yu Cai 0001, Erich F. Haratsch, Mark P. McCartney, Ken Mai	FPGA-Based Solid-State Drive Prototyping Platform.	FCCM	2011	DBLP DOI BibTeX RDF
1	Kunjan Patel, Séamas McGettrick, Chris J. Bleakley	SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing.	FCCM	2011	DBLP DOI BibTeX RDF
1	Robin Pottathuparambil, Jack Coyne, Jeffrey Allred, William Lynch, Vincent Natoli	Low-Latency FPGA Based Financial Data Feed Handler.	FCCM	2011	DBLP DOI BibTeX RDF
1	Oguzhan Erdem, Hoang Le, Viktor K. Prasanna, Cüneyt F. Bazlamaçci	Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Hoang Le, Weirong Jiang, Viktor K. Prasanna	Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression.	FCCM	2011	DBLP DOI BibTeX RDF
1	Edward Fernandez, Walid A. Najjar, Stefano Lonardi	String Matching in Hardware Using the FM-Index.	FCCM	2011	DBLP DOI BibTeX RDF
1	Janarbek Matai, Ali Irturk, Ryan Kastner	Design and Implementation of an FPGA-Based Real-Time Face Recognition System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Qiwei Jin, Wayne Luk, David B. Thomas	On Comparing Financial Option Price Solvers on FPGA.	FCCM	2011	DBLP DOI BibTeX RDF
1	Andy Gill, Tristan Bull, Daniel DePardo, Andrew Farmer, Ed Komp, Erik Perrins	Using Functional Programming to Generate an LDPC Forward Error Corrector.	FCCM	2011	DBLP DOI BibTeX RDF
1	Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto	Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth.	FCCM	2011	DBLP DOI BibTeX RDF
1	Robin Panda, Scott Hauck	Dynamic Communication in a Coarse Grained Reconfigurable Array.	FCCM	2011	DBLP DOI BibTeX RDF
1	Muhsen Owaida, Nikolaos Bellas, Konstantis Daloukas, Christos D. Antonopoulos	Synthesis of Platform Architectures from OpenCL Programs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings	HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping.	FCCM	2011	DBLP DOI BibTeX RDF
1	Lingkan Gong, Oliver Diessel	Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification.	FCCM	2011	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong	Mixed Precision Processing in Reconfigurable Systems.	FCCM	2011	DBLP DOI BibTeX RDF
1	Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson	Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.	FCCM	2011	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero	TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Anil Madhavapeddy, Satnam Singh	Reconfigurable Data Processing for Clouds.	FCCM	2011	DBLP DOI BibTeX RDF
1	Jainik Kathiara, Miriam Leeser	An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
1	Miaoqing Huang, Özlem Kilic	Reaping the Processing Potential of FPGA on Double-Precision Floating-Point Operations: An Eigenvalue Solver Case Study.	FCCM	2010	DBLP DOI BibTeX RDF
1	Gonzalo Carvajal, Sebastian Fischmeister	A TDMA Ethernet Switch for Dynamic Real-Time Communication.	FCCM	2010	DBLP DOI BibTeX RDF
1	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Energy-Aware Optimisation for Run-Time Reconfiguration.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jason Agron, David Andrews 0001	Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tayo Oguntebi, Sungpack Hong, Jared Casper, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun	FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.	FCCM	2010	DBLP DOI BibTeX RDF
1	Guiming Wu, Yong Dou, Gregory D. Peterson	Blocking LU Decomposition for FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Daniel Hefenbrock, Jason Oberg, Nhat Thanh, Ryan Kastner, Scott B. Baden	Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Andrew W. H. House, Manuel Saldaña, Paul Chow	Integrating High-Level Synthesis into MPI.	FCCM	2010	DBLP DOI BibTeX RDF
1	Anargyros Ilias, Kyprianos Papadimitriou, Apostolos Dollas	Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Ken Eguro	SIRC: An Extensible Reconfigurable Computing Communication API.	FCCM	2010	DBLP DOI BibTeX RDF
1	F. Javier Garrigós, J. Javier Martínez, Isidro Villó-Pérez, F. Javier Toledo, José Manuel Ferrández	Acceleration of a DWT-Based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform.	FCCM	2010	DBLP DOI BibTeX RDF
1	Faisal Khan, Nicholas Hosein, Scott Vernon, Soheil Ghiasi	BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic.	FCCM	2010	DBLP DOI BibTeX RDF
1	Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon	Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research.	FCCM	2010	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan	Accelerating the Nonuniform Fast Fourier Transform Using FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Hoang Le, Viktor K. Prasanna	A Memory-Efficient and Modular Approach for String Matching on FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jason R. Villarreal, Adrian Park 0002, Walid A. Najjar, Robert J. Halstead	Designing Modular Hardware Accelerators in C with ROCCC 2.0.	FCCM	2010	DBLP DOI BibTeX RDF
1	Dimitris Bouris, Antonis Nikitakis, Ioannis Papaefstathiou	Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm.	FCCM	2010	DBLP DOI BibTeX RDF
1	Barry Bond, Kerry Hammil, Lubomir Litchev, Satnam Singh	FPGA Circuit Synthesis of Accelerator Data-Parallel Programs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Christopher E. Neely, Gordon J. Brebner, Weijia Shang	ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Bernd Scheuermann	Design of a Reconfigurable Hybrid Database System.	FCCM	2010	DBLP DOI BibTeX RDF
1	Dirk Koch, Christian Beckhoff, Jim Tørresen	Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jimmy Xu, Nikhil Subramanian, Adam M. Alessio, Scott Hauck	Impulse C vs. VHDL for Accelerating Tomographic Reconstruction.	FCCM	2010	DBLP DOI BibTeX RDF
1	Yi Lu 0004, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev	A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems.	FCCM	2010	DBLP DOI BibTeX RDF
1	Daniel Ziener, Florian Baueregger, Jürgen Teich	Using the Power Side Channel of FPGAs for Communication.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jens-Peter Kaps, Rajesh Velegalati	DPA Resistant AES on FPGA Using Partial DDL.	FCCM	2010	DBLP DOI BibTeX RDF
1	Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich	Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems.	FCCM	2010	DBLP DOI BibTeX RDF
1	Yeim-Kuan Chang, Yi-Shang Lin, Cheng-Chien Su	A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification.	FCCM	2010	DBLP DOI BibTeX RDF
1	Jason Cong, Yi Zou	A Comparative Study on the Architecture Templates for Dynamic Nested Loops.	FCCM	2010	DBLP DOI BibTeX RDF
1	Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.	FCCM	2010	DBLP DOI BibTeX RDF
1	Junguk Cho, Bridget Benson, Sunsern Cheamanunkul, Ryan Kastner	Increased Performace of FPGA-Based Color Classification System.	FCCM	2010	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	Automated Precision Analysis: A Polynomial Algebraic Approach.	FCCM	2010	DBLP DOI BibTeX RDF
1	Markos Papadonikolakis, Christos-Savvas Bouganis	A Heterogeneous FPGA Architecture for Support Vector Machine Training.	FCCM	2010	DBLP DOI BibTeX RDF
1	J. L. Shafer, S. W. Schneider, Jon T. Butler, Pantelimon Stanica	Enumeration of Bent Boolean Functions by Reconfigurable Computer.	FCCM	2010	DBLP DOI BibTeX RDF
1	Hadi Parandeh-Afshar, Paolo Ienne	Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance.	FCCM	2010	DBLP DOI BibTeX RDF
1	Seunghun Jin, Dongkyun Kim, Duc Dung Nguyen, Jae Wook Jeon	Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA.	FCCM	2010	DBLP DOI BibTeX RDF
1	Sang Kyun Kim, Peter Leonard McMahon, Kunle Olukotun	A Large-Scale Architecture for Restricted Boltzmann Machines.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tomás Martínek, Matej Lexa	Hardware Acceleration of Approximate Tandem Repeat Detection.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tarek Ould Bachir, Jean-Pierre David	Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision.	FCCM	2010	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tim Todman, Qiang Liu 0011, Wayne Luk, George A. Constantinides	A Scripting Engine for Combining Design Transformations.	FCCM	2010	DBLP DOI BibTeX RDF
1	Ron Sass, Russell Tessier (eds.)	18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010	FCCM	2010	DBLP BibTeX RDF
1	Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan	More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control.	FCCM	2009	DBLP DOI BibTeX RDF	Solution Linear Systems, FPGA, Iterative Methods, Conjugate Gradient, MPC
1	Zachary K. Baker, Joshua S. Monson	In-situ FPGA Debug Driven by On-Board Microcontroller.	FCCM	2009	DBLP DOI BibTeX RDF	Extreme Environments, FPGA, Debugging, Space, JTAG
1	David B. Thomas, Wayne Luk	FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, spiking neural networks
1	G. Adam Covington, Glen Gibb, John W. Lockwood, Nick McKeown	A Packet Generator on the NetFPGA Platform.	FCCM	2009	DBLP DOI BibTeX RDF
1	Michael P. Caffrey, Keith Morgan, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael J. Wirthlin, William Howes, Daniel Richins	On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat).	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, fault tolerant computing, configurable computing
1	Philip Top, Maya B. Gokhale	Application Experiments: MPPA and FPGA.	FCCM	2009	DBLP DOI BibTeX RDF	Ambric, MPPA
1	David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport	Non-Preconditioned Conjugate Gradient on Cell and FPGA Based Hybrid Supercomputer Nodes.	FCCM	2009	DBLP DOI BibTeX RDF
1	Depeng Yang, Gregory D. Peterson, Husheng Li, Junqing Sun	An FPGA Implementation for Solving Least Square Problem.	FCCM	2009	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )