Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Nicolae Bogdan Grigore, Dirk Koch |
Placing partially reconfigurable stream processing applications on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Siddharth Advani, Yasuki Tanabe, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan |
A scalable architecture for multi-class visual object detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Stefan Wonneberger, Peter Mühlfellner, Pedro Ceriotti, Thorsten Graf 0001, Rolf Ernst |
Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zdravko Panjkov, Andreas Wasserbauer, Timm Ostermann, Richard Hagelauer |
Hybrid FPGA debug approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Hosseinabady, José Luis Núñez-Yáñez |
Energy optimization of FPGA-based stream-oriented computing with power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz |
Design and simulation tools for Embedded NOCs on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mudhar Bin Rabieah, Christos-Savvas Bouganis |
FPGA based nonlinear Support Vector Machine training using an ensemble learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Eddie Hung |
Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Cilardo |
Variable-latency signed addition on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ali Ahari, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori |
Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nachiket Kapre, Jan Gray |
Hoplite: Building austere overlay NoCs for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano |
Reduction calculator in an FPGA based switching Hub for high performance clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zoltan Lehoczky, Richárd Tóth, Krisztian Somogyi |
High-level FPGA logic synthesis from .NET programs for software developers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nuno Neves 0002, Pedro Tomás, Nuno Roma |
Efficient data-stream management for shared-memory many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sebastian Friston, Anthony Steed, Simon Tilbury, Georgi Gaydadjiev |
Ultra low latency dataflow renderer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura |
Data-triggered breakpoint for in-circuit debug without re-implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hao Liang 0003, Wei Zhang 0012, Sharad Sinha, Yi-Chung Chen, Hai Li 0001 |
Hierarchical library based power estimator for versatile FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Büter, Alberto García Ortiz, A. Ali, S. Mahmood, S. Arefin, V. V. Parsi Sreenivas, R. B. Bergman |
A rapid prototyping framework for nano-photonic accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jin Hee Kim, Jason Helge Anderson |
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nizar Dahir, Pedro B. Campos, Gianluca Tempesti, Martin Trefzer, Andrew M. Tyrrell |
Characterisation of feasibility regions in FPGAs under adaptive DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | |
25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015 ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![IEEE, 978-0-9934-2800-5 The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
1 | Xiaotong Li, Benjamin Carrión Schäfer |
Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne |
A technology mapper for depth-constrained FPGA logic cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono |
rrBox: A remote dynamically reconfigurable network processing middlebox. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Peter Y. K. Cheung, Wayne Luk, Cristina Silvano |
Preface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-2, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zsolt István, David Sidler, Gustavo Alonso |
Building a distributed key-value store with FPGA-based microservers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Meena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan |
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
Accurate power analysis for near-Vt RRAM-based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Stylianos I. Venieris, Grigorios Mingas, Christos-Savvas Bouganis |
Towards heterogeneous solvers for large-scale linear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar |
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris |
High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-2, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Thiem Van Chu, Shimpei Sato, Kenji Kise |
Ultra-fast NoC emulation on a single FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Kai-Uwe Irrgang, Thomas B. Preußer |
An LZ77-style bit-level compression for trace data compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto |
Enhancing stochastic computations via process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-7, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer |
Scavenger: Automating the construction of application-optimized memory hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yoko Sogabe, Tsutomu Maruyama |
A variable length hash method for faster short read mapping on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano |
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Stephan Werner 0002, Leonard Masing, Fabian Lesniak, Jürgen Becker 0001 |
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hao Liang 0003, Sharad Sinha, Rakesh Warrier, Wei Zhang 0012 |
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yaman Umuroglu, Donn Morrison, Magnus Jahre |
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica |
PushPush: Seamless integration of hardware and software objects via function calls over AXI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang 0002 |
Significant papers from the first 25 years of the FPL conference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-3, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Giacomo Valente |
A framework for integrated monitoring of real-time embedded SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-2, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alric Althoff, Ryan Kastner |
A scalable FPGA architecture for nonnegative least squares problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zakarya Guettatfi, Omar Kermia, Abdelhakim Khouas |
Over effective hard real-time hardware tasks scheduling and allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-2, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chaohui Du, Guoqiang Bai 0001 |
Towards efficient discrete Gaussian sampling for lattice-based cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Stefano Di Carlo, Paolo Prinetto, Pascal Trotta, Jan Andersson |
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nachiket Kapre, Jayakrishnan Selva Kumar, Parjanya Gupta, Sagar Shrishailappa Masuti, Sylvain Barbot |
Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Timm Bostelmann, Sergei Sawitzki |
Towards a guided design flow for heterogeneous reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-2, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Oleg Petelin, Vaughn Betz |
Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zia Uddin Ahamed Khan, Mohammed Benaissa |
High speed ECC implementation on FPGA over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ze-ke Wang, Bingsheng He, Wei Zhang 0012 |
A study of data partitioning on OpenCL-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Petr Pfeifer |
AmBRAMs - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi 0001 |
An efficient reconfigurable architecture by characterizing most frequent logic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Chadjiminas, Christos Kyrkou, Theocharis Theocharides, Maria K. Michael, Christos Ttofis |
In-field vulnerability analysis of hardware-accelerated computer vision applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk |
Efficient assembly for high order unstructured FEM meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Roel Oomen, Tuan D. A. Nguyen, Akash Kumar 0001, Henk Corporaal |
An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Khalid Javeed, Xiaojun Wang 0001, Mike Scott |
Serial and parallel interleaved modular multipliers on FPGA platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-4, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gabriel Weisz, James C. Hoe |
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-8, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Marco Indaco, Fabio Lauri, Andrea Miele, Pascal Trotta |
An efficient many-core architecture for Elliptic Curve Cryptography security assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, pp. 1-6, 2015, IEEE, 978-0-9934-2800-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Matthew Jacobsen, Siddarth Sampangi, Yoav Freund, Ryan Kastner |
Improving FPGA accelerated tracking with multiple online trained classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-7, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey B. Goeders, Steven J. E. Wilton |
Effective FPGA debug for high-level synthesis generated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar |
Application specific multi-port memory customization in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Bouthaina Damak, Rachid Benmansour, Smaïl Niar, Mouna Baklouti, Mohamed Abid |
A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Hosseinabady, José Luis Núñez-Yáñez |
Run-time power gating in hybrid ARM-FPGA devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Roland Dobai |
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jason Xin Zheng, Dongfang Li, Miodrag Potkonjak |
A secure and unclonable embedded system using instruction-level PUF authentication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen 0014, Fei Wang, Tongqiang Gao, Haigang Yang |
A survey of open source processors for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Shyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari, Akash Kumar 0001 |
Multi-directional error correction schemes for SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf |
Pipelined reconfigurable multiplication with constants on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jens Huthmann, Julian Oppermann, Andreas Koch 0001 |
Automatic high-level synthesis of multi-threaded hardware accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Qian Zhao 0001, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Shinya Takamaeda-Yamazaki, Kenji Kise |
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Thinh Hung Pham, Suhaib A. Fahmy, Ian Vince McLoughlin |
Efficient multi-standard cognitive radios on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-2, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Dajung Lee, Janarbek Matai, Brad T. Weals, Ryan Kastner |
High throughput channel tracking for JTRS wireless channel emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Matthew Naylor, Simon W. Moore |
Rapid codesign of a soft vector processor and its compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise |
Ultrasmall: The smallest MIPS soft processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Bogdan Pasca 0001 |
Low-cost multiplier-based FPU for embedded processing on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Huriaux, Olivier Sentieys, Russell Tessier |
FPGA architecture support for heterogeneous, relocatable partial bitstreams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang |
Exploring architecture parameters for dual-output LUT based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fatemeh Eslami, Steven J. E. Wilton |
Incremental distributed trigger insertion for efficient FPGA debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | A. Theodore Markettos, Paul James Fox, Simon W. Moore, Andrew W. Moore 0002 |
Interconnect for commodity FPGA clusters: Standardized or customized? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So |
Mixed-architecture process scheduling on tightly coupled reconfigurable computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Honlian Su, Yu Fujita, Hideharu Amano |
Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas |
High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich |
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri |
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Marlon Wijeyasinghe, David Thomas 0001 |
Using high-level knowledge to enhance data channels in FPGA streaming systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-2, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Moritz Schmid, Nicolas Apelt, Frank Hannig, Jürgen Teich |
An image processing library for C-based high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Mário P. Véstias, Horácio C. Neto |
Trends of CPU, GPU and FPGA for high-performance computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson |
Source-level debugging for FPGA high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Nam Ho, Paul Kaufmann, Marco Platzner |
A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Bajaj Ronak, Suhaib A. Fahmy |
Efficient mapping of mathematical expressions into DSP blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek |
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Teng Xu 0001, Miodrag Potkonjak |
Robust and flexible FPGA-based digital PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Kizheppatt Vipin, Suhaib A. Fahmy |
DyRACT: A partial reconfiguration enabled accelerator and test platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-7, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Unai Martinez-Corral, Koldo Basterretxea, Raul Finker |
Scalable parallel architecture for singular value decomposition of large matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
Pattern-based FPGA logic block and clustering algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Juan Valverde, Alfonso Rodríguez 0002, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|