Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1395-1415, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Takahiro Kumura, Masao Ikekawa, Makoto Yoshida, Ichiro Kuroda |
VLIW DSP for mobile applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Mag. ![In: IEEE Signal Process. Mag. 19(4), pp. 10-21, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Oliver P. Sohm, David R. Bull, Cedric Nishan Canagarajah |
Efficient methodology for hand-coding video algorithms for VLIW-type processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. Image Commun. ![In: Signal Process. Image Commun. 17(4), pp. 305-325, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 102-111, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
16 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Optimizing Loop Performance for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 271-280, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon |
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1128, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, S. Balakrishanan |
Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002, pp. 43-48, 2002, IEEE Computer Society, 0-7695-1807-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
16 | Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan |
On the Benefits of Speculative Trace Scheduling in VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '02, June 24 - 27, 2002, Las Vegas, Nevada, USA, Volume 2, pp. 822-828, 2002, CSREA Press, 1-892512-88-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
16 | Won-Kee Hong, Shin-Dug Kim |
A Performance and Power Efficient Instruction Cache for VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '02, June 24 - 27, 2002, Las Vegas, Nevada, USA, Volume 4, pp. 1883-1889, 2002, CSREA Press, 1-892512-90-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
16 | Daniele Bagni, Antonio Borneo, Luca Celetto |
Efficient IDCT implementations on VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 11th European Signal Processing Conference, EUSIPCO 2002, Toulouse, France, September 3-6, 2002, pp. 1-4, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
16 | F. Jesús Sánchez, Antonio González 0001 |
Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 3, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
16 | Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá |
Functional units with conditional input/output behavior in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 822, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Andrei Sergeevich Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven |
PRMDL: a machine description language for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 821, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
An implementation for test-time reduction in VLIW transport-triggered architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001, pp. 106-113, 2001, IEEE Computer Society, 0-7695-1017-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Sid Ahmed Ali Touati |
Register Saturation in Superscalar and VLIW Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 213-228, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Sohail Sadiq, Shoab Ahmed Khan |
Scheduling of Digital Signal Processing Algorithms on StarCore VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCS ![In: Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA, pp. 196-199, 2001, ISCA, 1-880843-39-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
16 | Yuan Xie 0001, Haris Lekatsas, Wayne H. Wolf |
Code Compression for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Data Compression Conference ![In: Data Compression Conference, DCC 2001, Snowbird, Utah, USA, March 27-29, 2001., pp. 525, 2001, IEEE Computer Society, 0-7695-1031-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen |
Phase coupled operation assignment for VLIW processors with distributed register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001., pp. 118-123, 2001, ACM / IEEE Computer Society, 1-58113-418-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Radu Muresan, Catherine H. Gebotys |
Current consumption dynamics at instruction and program level for a VLIW DSP processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001., pp. 130-135, 2001, ACM / IEEE Computer Society, 1-58113-418-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OM@PLDI ![In: Proceedings of the 2001 ACM SIGPLAN Workshop on Optimization of Middleware and Distributed Systems, OM '01, Snow Bird, Utah, USA, pp. 138-144, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | William R. Mark, Kekoa Proudfoot |
Compiling to a VLIW Fragment Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Graphics Hardware ![In: Proceedings of the 2001 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, Los Angeles, CA, USA, August 12-13, 2001, pp. 47-55, 2001, The Eurographics Association, 158113407X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Cagdas Akturan, Margarida F. Jacome |
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001, pp. 112-118, 2001, IEEE Computer Society, 0-7803-7249-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo |
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 141-148, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Han-Saem Yun, Jihong Kim 0001 |
Power-aware modulo scheduling for high-performance VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 40-45, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
A Framework for Energy Estimation of VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 40-45, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte |
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1-3, 2001. Revised Papers, pp. 223-238, 2001, Springer, 3-540-04029-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
High-Quality Operation Binding for Clustered VLIW Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 702-707, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Miroslav N. Velev, Randal E. Bryant |
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 226-231, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Margarida F. Jacome, Gustavo de Veciana, Satish Pillai |
Clustered VLIW Architectures with Predicated Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 696-701, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Alberto Ferreira de Souza, Peter Rounce |
Dynamically Scheduling VLIW Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 60(12), pp. 1480-1511, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Won-Kee Hong, Shin-Dug Kim |
A section cache system designed for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 46(14), pp. 1293-1308, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Miroslav N. Velev |
Formal Verification of VLIW Microprocessors with Speculative Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 12th International Conference, CAV 2000, Chicago, IL, USA, July 15-19, 2000, Proceedings, pp. 296-311, 2000, Springer, 3-540-67770-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami |
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 218, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Two-level hierarchical register file organization for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 137-146, 2000, ACM/IEEE Computer Society, 0-7695-0924-x. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | F. Jesús Sánchez, Antonio González 0001 |
Modulo scheduling for a fully-distributed clustered VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 124-133, 2000, ACM/IEEE Computer Society, 0-7695-0924-x. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Yong Zhang, Kai-Kuang Ma, Qingdong Yao |
Novel video signal processor with VLIW-controlled SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VCIP ![In: Visual Communications and Image Processing 2000, Perth, Australia, June 20, 2000, pp. 932-941, 2000, SPIE, 0-8194-3703-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
16 | Shoab Ahmad Khan, Malik M. Saqib, Sherjil Ahmed |
Parallel Viterbi algorithm for a VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing. ICASSP 2000, 5-9 June, 2000, Hilton Hotel and Convention Center, Istanbul, Turkey, pp. 3390-3393, 2000, IEEE, 0-7803-6293-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | M. Beardo, Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto |
An approach to functional testing of VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 29-33, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel |
Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28 - March 1, 2000, pp. 177-185, 2000, VDE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
16 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
Power Exploration for Embedded VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 498-503, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii |
Exploring Performance Tradeoffs for Clustered VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 504-510, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda |
Novel VLIW code compaction method for a 3D geometry processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, pp. 555-558, 2000, IEEE, 0-7803-5809-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Sang-Joon Nam, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, Chong-Min Kyung |
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, pp. 551-554, 2000, IEEE, 0-7803-5809-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park |
Multi-thread VLIW processor architecture for HDTV decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, pp. 559-562, 2000, IEEE, 0-7803-5809-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Ivano Barbieri, Massimo Bariani, Marco Raggio |
A VLIW Architecture Simulator Innovative Approach for HW-SW Co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Conference on Multimedia and Expo (III) ![In: 2000 IEEE International Conference on Multimedia and Expo, ICME 2000, New York, NY, USA, July 30 - August 2, 2000, pp. 1375-1378, 2000, IEEE Computer Society, 0-7803-6536-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik |
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2000, San Jose, California, USA, November 7-18, 2000, pp. 157-164, 2000, ACM, 1-58113-338-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | B. Ramakrishna Rau, Vinod Kathail, Shail Aditya |
Machine-Description Driven Compilers for EPIC and VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 4(2-3), pp. 71-118, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito 0005, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada |
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(11), pp. 1619-1626, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Sang-Joon Nam, Young-Su Kwon, Yeon-Ho Im, Kyung-Ku Kang, Chong-Min Kyung |
DIVA: dual-issue VLIW architecture with media instructions for image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Consumer Electron. ![In: IEEE Trans. Consumer Electron. 45(1), pp. 192-202, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Kiyoshige Nakamura, Keiichi Sakai, Tadashi Ae |
Multimedia data processing using a VLIW hardware stack processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 30(10), pp. 34-40, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami |
A DAG-Based Design Approach for Reconfigurable VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 778-779, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Alberto Ferreira de Souza, Peter Rounce |
Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 7th International Conference, HPCN Europe 1999, Amsterdam, The Netherlands, April 12-14, 1999, Proceedings, pp. 1203-1206, 1999, Springer, 3-540-65821-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Todd D. Hodes, Adrian Freed |
Second-order Recursive Oscillators for Musical Additive Synthesis Applications on SIMD and VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMC ![In: Proceedings of the 1999 International Computer Music Conference, ICMC 1999, Beijing, China, October 22-27, 1999, 1999, Michigan Publishing. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
16 | Oliver P. Sohm, David R. Bull, Cedric Nishan Canagarajah |
Fast 2D-DCT implementations for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMSP ![In: Third IEEE Workshop on Multimedia Signal Processing, MMSP 1999, Copenhagen, Denmark, September 13-15, 1999, pp. 655-660, 1999, IEEE, 0-7803-5610-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan |
Resource constrained dataflow retiming heuristics for VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999, pp. 12-16, 1999, ACM, 1-58113-132-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Alberto Ferreira de Souza |
Integer performance evaluation of the dynamically trace scheduled VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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1999 |
RDF |
|
16 | Nat Seshan |
High VelociTI processing [Texas Instruments VLIW DSP architecture]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Mag. ![In: IEEE Signal Process. Mag. 15(2), pp. 86-101, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Konstantinos Konstantinides |
VLIW Architecture For Media Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Mag. ![In: IEEE Signal Process. Mag. 15(2), pp. 16-19, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Alberto Ferreira de Souza, Peter Rounce |
Dynamically Trace Scheduled VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, International Conference and Exhibition, HPCN Europe 1998, Amsterdam, The Netherlands, April 21-23, 1998, Proceedings, pp. 993-995, 1998, Springer, 3-540-64443-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham |
Partitioned Schedules for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS/SPDP ![In: 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30 - April 3, 1998, Orlando, Florida, USA, Proceedings, pp. 386-391, 1998, IEEE Computer Society, 0-8186-8403-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Zhao Wu, Wayne H. Wolf |
Data-Path Synthesis of VLIW Video Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 11th International Symposium on System Synthesis, ISSS '98, Hsinchu, Taiwan, December 2-4, 1998., pp. 96-104, 1998, ACM / IEEE Computer Society, 0-8186-8623-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | T. Buchholz, Gunter Haug, Udo Kebschull, Gernot Koch, Wolfgang Rosenstiel |
Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Workshop on Rapid System Prototyping ![In: Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), Leuven, Belgium, June 3-5, 1998, pp. 70-, 1998, IEEE Computer Society, 0-8186-8479-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik R. Altman, Krishnan Kailas, Terry Bright |
An eight-issue tree-VLIW processor for dynamic binary translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 488-495, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Rizos Sakellariou, Christine Eisenbeis, Peter M. W. Knijnenburg |
Efficient implementation of the row-column 8×8 IDCT on VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 9th European Signal Processing Conference, EUSIPCO 1998, Island of Rhodes, Greece, 8-11 September, 1998, pp. 1-4, 1998, IEEE, 978-960-7620-06-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
16 | Marcio Merino Fernandes |
A clustered VLIW architecture based on queue register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1998 |
RDF |
|
16 | Jörg Wilberg, Raul Camposano |
VLIW Processor Codesign for Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 2(1), pp. 79-119, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Chris Basoglu, Woobin Lee, Yongmin Kim 0001 |
An Efficient FFT Algorithm for Superscalar and VLIW Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Imaging ![In: Real Time Imaging 3(6), pp. 441-453, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Martti Forsell |
MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Univers. Comput. Sci. ![In: J. Univers. Comput. Sci. 3(9), pp. 1037-1055, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Jaime H. Moreno, Mayan Moudgill, Kemal Ebcioglu, Erik R. Altman, C. Brian Hall, Rene Miranda, Shyh-Kwei Chen, Arkady Polyak |
Simulation/evaluation environment for a VLIW processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 41(3), pp. 287-302, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Thomas M. Conte, Sumedh W. Sathaye |
Optimization of VLIW compatibility systems employing dynamic rescheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 25(2), pp. 83-112, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Alberto Ferreira de Souza, Edil S. T. Fernandes, Andrew Wolfe |
On the balance of VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 43(1-5), pp. 15-22, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
16 | Henk Corporaal |
Microprocessor architectures - from VLIW to TTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1997 |
RDF |
|
16 | Johannes Kneip, Mladen Berekovic, Peter Pirsch |
An algorithm-hardware-system approach to VLIW multimedia processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMSP ![In: First IEEE Workshop on Multimedia Signal Processing, MMSP 1997, Princeton, New Jersey, USA, June 23-25, 1997, pp. 433-438, 1997, IEEE, 0-7803-3780-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Russell E. Henning, Chaitali Chakrabarti |
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 571-576, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Mayan Moudgill |
Implementing an experimental VLIW compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1997 workshop on Computer architecture education, WCAE@HPCA 1997, San Antonio, Texas, USA, February 1997, pp. 7, 1997, ACM, 978-1-4503-4739-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Jean-Paul Theis, Lothar Thiele |
VLIW-Processors under Periodic Real Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 191-199, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Risc architecture, frontend compilers, embedded systems |
16 | Shusuke Okamoto, Masahiro Sowa |
Hybrid Processor Based on VLIW and PN-Superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1996, August 9-11, 1996, Sunnyvale, California, USA, pp. 623-632, 1996, CSREA Press, 0-9648666-4-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP BibTeX RDF |
|
16 | Kiyoshige Nakamura, Keiichi Sakai, Tadashi Ae |
A VLIW Processor For Real-Time Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSPA ![In: Fourth International Symposium on Signal Processing and Its Applications, ISSPA 1996, Royal Pines Resort, Gold Cost, Queensland, Australia, August 25-30, pp. 664-667, 1996, IEEE, 0-7803-4114-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Capitanio, Alexandru Nicolau, Nikil D. Dutt |
A hypergraph-based model for port allocation on multiple-register-file VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 23(6), pp. 499-513, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero |
Automatic generation of loop scheduling for VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, PACT '95, Limassol, Cyprus, June 27-29, 1995, pp. 306-309, 1995, IFIP Working Group on Algol / ACM. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
16 | Thomas M. Conte, Sumedh W. Sathaye |
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 208-218, 1995, ACM / IEEE Computer Society, 0-8186-7349-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | James Radigan, Pohua P. Chang, Utpal Banerjee |
Integer Loop Code Generation for VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 8th International Workshop, LCPC'95, Columbus, Ohio, USA, August 10-12, 1995, Proceedings, pp. 318-330, 1995, Springer, 3-540-60765-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | John Lenell, Nader Bagherzadeh |
A performance comparison of several superscalar processor models with a VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 18(3), pp. 131-139, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Marc Pouzet |
Fine Grain Parallelisation of Functional Programs for VLIW or Super-scalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Applications in Parallel and Distributed Computing ![In: Applications in Parallel and Distributed Computing, Proceedings of the IFIP WG10.3 Working Conference on Applications in Parallel and Distributed Computing, Caracas, Venezuela, 18-22 April, 1994, pp. 195-204, 1994, North-Holland, 0-444-81870-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
16 | Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé |
Using Sacks to Organize Registers in VLIW Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 628-639, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu |
An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1994 International Conference on Parallel Processing, North Carolina State University, NC, USA, August 15-19, 1994. Volume I: Architecture., pp. 285-292, 1994, CRC Press, 0-8493-2493-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau |
Partitioning of Variables for Multiple-Register-File VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1994 International Conference on Parallel Processing, North Carolina State University, NC, USA, August 15-19, 1994. Volume I: Architecture., pp. 298-301, 1994, CRC Press, 0-8493-2493-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery |
The superblock: An effective technique for VLIW and superscalar compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 7(1-2), pp. 229-248, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Michael A. Schuette, John Paul Shen |
Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 7(1-2), pp. 249-271, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Bogong Su, Jian Wang 0046, Zhizhong Tang, Chihong Zhang, Wei Zhao |
URPR-1: A single-chip VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 39(1), pp. 25-41, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Peter Pfahler, Christof Nagel, Franz-Josef Rammig, Uwe Kastens |
Design of a VLIW architecture constructed from standard RISC chips: A case study of hardware/software codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 38(1-5), pp. 61-68, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale |
Addressing mechanisms for VLIW and superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 39(2-5), pp. 75-78, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | H. Fatih Ugurdag, Christos A. Papachristou |
A VLIW architecture based on shifting register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 263-268, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | John Lenell, Nader Bagherzadeh |
A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: The Seventh International Parallel Processing Symposium, Proceedings, Newport Beach, California, USA, April 13-16, 1993., pp. 44-48, 1993, IEEE Computer Society, 0-8186-3442-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa |
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 243-254, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | Soo-Mook Moon, Kemal Ebcioglu, Ashok K. Agrawala |
Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 229-242, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | G. Menez, Michel Auguin, Fernand Boéri, C. Carrière |
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 217-228, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | Soo-Mook Moon, Kemal Ebcioglu |
On Performance, Efficiency of VLIW and Superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (2) ![In: Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume II: Software., pp. 283-287, 1993, CRC Press, 0-8493-8985-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | C. Carrière, Michel Auguin, Fernand Boéri, G. Menez |
A comparison study of minimization methods of unit interconnection in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 35(1-5), pp. 595-602, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Tokuzo Kiyohara, John C. Gyllenhaal |
Code scheduling for VLIW/superscalar processors with limited register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992, pp. 197-201, 1992, ACM / IEEE Computer Society, 0-8186-3175-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|