Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
16	Takahiro Kumura, Masao Ikekawa, Makoto Yoshida, Ichiro Kuroda	VLIW DSP for mobile applications.	IEEE Signal Process. Mag.	2002	DBLP DOI BibTeX RDF
16	Oliver P. Sohm, David R. Bull, Cedric Nishan Canagarajah	Efficient methodology for hand-coding video algorithms for VLIW-type processors.	Signal Process. Image Commun.	2002	DBLP DOI BibTeX RDF
16	Christoph W. Keßler, Andrzej Bednarski	Optimal integrated code generation for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection
16	Yi Qian, Steve Carr 0001, Philip H. Sweany	Optimizing Loop Performance for Clustered VLIW Architectures.	IEEE PACT	2002	DBLP DOI BibTeX RDF
16	Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon	An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.	DATE	2002	DBLP DOI BibTeX RDF
16	Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, S. Balakrishanan	Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors.	SBCCI	2002	DBLP BibTeX RDF
16	Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan	On the Benefits of Speculative Trace Scheduling in VLIW Processors.	PDPTA	2002	DBLP BibTeX RDF
16	Won-Kee Hong, Shin-Dug Kim	A Performance and Power Efficient Instruction Cache for VLIW.	PDPTA	2002	DBLP BibTeX RDF
16	Daniele Bagni, Antonio Borneo, Luca Celetto	Efficient IDCT implementations on VLIW processors.	EUSIPCO	2002	DBLP BibTeX RDF
16	F. Jesús Sánchez, Antonio González 0001	Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache .	J. Instr. Level Parallelism	2001	DBLP BibTeX RDF
16	Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá	Functional units with conditional input/output behavior in VLIW processors.	DATE	2001	DBLP DOI BibTeX RDF
16	Andrei Sergeevich Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven	PRMDL: a machine description language for clustered VLIW architectures.	DATE	2001	DBLP DOI BibTeX RDF
16	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	An implementation for test-time reduction in VLIW transport-triggered architectures.	ETW	2001	DBLP DOI BibTeX RDF
16	Sid Ahmed Ali Touati	Register Saturation in Superscalar and VLIW Codes.	CC	2001	DBLP DOI BibTeX RDF
16	Muhammad Sohail Sadiq, Shoab Ahmed Khan	Scheduling of Digital Signal Processing Algorithms on StarCore VLIW DSP.	PDCS	2001	DBLP BibTeX RDF
16	Yuan Xie 0001, Haris Lekatsas, Wayne H. Wolf	Code Compression for VLIW Processors.	Data Compression Conference	2001	DBLP DOI BibTeX RDF
16	Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen	Phase coupled operation assignment for VLIW processors with distributed register files.	ISSS	2001	DBLP DOI BibTeX RDF
16	Radu Muresan, Catherine H. Gebotys	Current consumption dynamics at instruction and program level for a VLIW DSP processor.	ISSS	2001	DBLP DOI BibTeX RDF
16	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture.	OM@PLDI	2001	DBLP DOI BibTeX RDF
16	William R. Mark, Kekoa Proudfoot	Compiling to a VLIW Fragment Pipeline.	Workshop on Graphics Hardware	2001	DBLP DOI BibTeX RDF
16	Cagdas Akturan, Margarida F. Jacome	CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors.	ICCAD	2001	DBLP DOI BibTeX RDF
16	Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo	Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.	CASES	2001	DBLP DOI BibTeX RDF
16	Han-Saem Yun, Jihong Kim 0001	Power-aware modulo scheduling for high-performance VLIW processors.	ISLPED	2001	DBLP DOI BibTeX RDF
16	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	A Framework for Energy Estimation of VLIW Architecture.	ICCD	2001	DBLP DOI BibTeX RDF
16	Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte	Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors.	LCPC	2001	DBLP DOI BibTeX RDF
16	Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana	High-Quality Operation Binding for Clustered VLIW Datapaths.	DAC	2001	DBLP DOI BibTeX RDF
16	Miroslav N. Velev, Randal E. Bryant	Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors.	DAC	2001	DBLP DOI BibTeX RDF
16	Margarida F. Jacome, Gustavo de Veciana, Satish Pillai	Clustered VLIW Architectures with Predicated Switching.	DAC	2001	DBLP DOI BibTeX RDF
16	Alberto Ferreira de Souza, Peter Rounce	Dynamically Scheduling VLIW Instructions.	J. Parallel Distributed Comput.	2000	DBLP DOI BibTeX RDF
16	Won-Kee Hong, Shin-Dug Kim	A section cache system designed for VLIW architectures.	J. Syst. Archit.	2000	DBLP DOI BibTeX RDF
16	Miroslav N. Velev	Formal Verification of VLIW Microprocessors with Speculative Execution.	CAV	2000	DBLP DOI BibTeX RDF
16	Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami	Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
16	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Two-level hierarchical register file organization for VLIW processors.	MICRO	2000	DBLP DOI BibTeX RDF
16	F. Jesús Sánchez, Antonio González 0001	Modulo scheduling for a fully-distributed clustered VLIW architecture.	MICRO	2000	DBLP DOI BibTeX RDF
16	Yong Zhang, Kai-Kuang Ma, Qingdong Yao	Novel video signal processor with VLIW-controlled SIMD architecture.	VCIP	2000	DBLP BibTeX RDF
16	Shoab Ahmad Khan, Malik M. Saqib, Sherjil Ahmed	Parallel Viterbi algorithm for a VLIW DSP.	ICASSP	2000	DBLP DOI BibTeX RDF
16	M. Beardo, Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto	An approach to functional testing of VLIW architectures.	HLDVT	2000	DBLP DOI BibTeX RDF
16	Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel	Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren.	MBMV	2000	DBLP BibTeX RDF
16	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Power Exploration for Embedded VLIW Architectures.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii	Exploring Performance Tradeoffs for Clustered VLIW ASIPs.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda	Novel VLIW code compaction method for a 3D geometry processor.	CICC	2000	DBLP DOI BibTeX RDF
16	Sang-Joon Nam, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, Chong-Min Kyung	FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit.	CICC	2000	DBLP DOI BibTeX RDF
16	Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park	Multi-thread VLIW processor architecture for HDTV decoding.	CICC	2000	DBLP DOI BibTeX RDF
16	Ivano Barbieri, Massimo Bariani, Marco Raggio	A VLIW Architecture Simulator Innovative Approach for HW-SW Co-design.	IEEE International Conference on Multimedia and Expo (III)	2000	DBLP DOI BibTeX RDF
16	Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik	Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.	CASES	2000	DBLP DOI BibTeX RDF
16	B. Ramakrishna Rau, Vinod Kathail, Shail Aditya	Machine-Description Driven Compilers for EPIC and VLIW Processors.	Des. Autom. Embed. Syst.	1999	DBLP DOI BibTeX RDF
16	Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito 0005, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada	A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
16	Sang-Joon Nam, Young-Su Kwon, Yeon-Ho Im, Kyung-Ku Kang, Chong-Min Kyung	DIVA: dual-issue VLIW architecture with media instructions for image processing.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
16	Kiyoshige Nakamura, Keiichi Sakai, Tadashi Ae	Multimedia data processing using a VLIW hardware stack processor.	Syst. Comput. Jpn.	1999	DBLP DOI BibTeX RDF
16	Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami	A DAG-Based Design Approach for Reconfigurable VLIW Processors.	DATE	1999	DBLP DOI BibTeX RDF
16	Alberto Ferreira de Souza, Peter Rounce	Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture.	HPCN	1999	DBLP DOI BibTeX RDF
16	Todd D. Hodes, Adrian Freed	Second-order Recursive Oscillators for Musical Additive Synthesis Applications on SIMD and VLIW Processors.	ICMC	1999	DBLP BibTeX RDF
16	Oliver P. Sohm, David R. Bull, Cedric Nishan Canagarajah	Fast 2D-DCT implementations for VLIW processors.	MMSP	1999	DBLP DOI BibTeX RDF
16	Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan	Resource constrained dataflow retiming heuristics for VLIW ASIPs.	CODES	1999	DBLP DOI BibTeX RDF
16	Alberto Ferreira de Souza	Integer performance evaluation of the dynamically trace scheduled VLIW.		1999	RDF
16	Nat Seshan	High VelociTI processing [Texas Instruments VLIW DSP architecture].	IEEE Signal Process. Mag.	1998	DBLP DOI BibTeX RDF
16	Konstantinos Konstantinides	VLIW Architecture For Media Processing.	IEEE Signal Process. Mag.	1998	DBLP DOI BibTeX RDF
16	Alberto Ferreira de Souza, Peter Rounce	Dynamically Trace Scheduled VLIW Architectures.	HPCN	1998	DBLP DOI BibTeX RDF
16	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham	Partitioned Schedules for Clustered VLIW Architectures.	IPPS/SPDP	1998	DBLP DOI BibTeX RDF
16	Zhao Wu, Wayne H. Wolf	Data-Path Synthesis of VLIW Video Signal Processors.	ISSS	1998	DBLP DOI BibTeX RDF
16	T. Buchholz, Gunter Haug, Udo Kebschull, Gernot Koch, Wolfgang Rosenstiel	Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures.	International Workshop on Rapid System Prototyping	1998	DBLP DOI BibTeX RDF
16	Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik R. Altman, Krishnan Kailas, Terry Bright	An eight-issue tree-VLIW processor for dynamic binary translation.	ICCD	1998	DBLP DOI BibTeX RDF
16	Rizos Sakellariou, Christine Eisenbeis, Peter M. W. Knijnenburg	Efficient implementation of the row-column 8×8 IDCT on VLIW architectures.	EUSIPCO	1998	DBLP BibTeX RDF
16	Marcio Merino Fernandes	A clustered VLIW architecture based on queue register files.		1998	RDF
16	Jörg Wilberg, Raul Camposano	VLIW Processor Codesign for Video Processing.	Des. Autom. Embed. Syst.	1997	DBLP DOI BibTeX RDF
16	Chris Basoglu, Woobin Lee, Yongmin Kim 0001	An Efficient FFT Algorithm for Superscalar and VLIW Processor Architectures.	Real Time Imaging	1997	DBLP DOI BibTeX RDF
16	Martti Forsell	MTAC - A Multithreaded VLIW Architecture for PRAM Simulation.	J. Univers. Comput. Sci.	1997	DBLP DOI BibTeX RDF
16	Jaime H. Moreno, Mayan Moudgill, Kemal Ebcioglu, Erik R. Altman, C. Brian Hall, Rene Miranda, Shyh-Kwei Chen, Arkady Polyak	Simulation/evaluation environment for a VLIW processor architecture.	IBM J. Res. Dev.	1997	DBLP DOI BibTeX RDF
16	Thomas M. Conte, Sumedh W. Sathaye	Optimization of VLIW compatibility systems employing dynamic rescheduling.	Int. J. Parallel Program.	1997	DBLP DOI BibTeX RDF
16	Alberto Ferreira de Souza, Edil S. T. Fernandes, Andrew Wolfe	On the balance of VLIW architectures.	J. Syst. Archit.	1997	DBLP BibTeX RDF
16	Henk Corporaal	Microprocessor architectures - from VLIW to TTA.		1997	RDF
16	Johannes Kneip, Mladen Berekovic, Peter Pirsch	An algorithm-hardware-system approach to VLIW multimedia processors.	MMSP	1997	DBLP DOI BibTeX RDF
16	Russell E. Henning, Chaitali Chakrabarti	High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder.	ICCD	1997	DBLP DOI BibTeX RDF
16	Mayan Moudgill	Implementing an experimental VLIW compiler.	WCAE@HPCA	1997	DBLP DOI BibTeX RDF
16	Jean-Paul Theis, Lothar Thiele	VLIW-Processors under Periodic Real Time Constraints.	ICCD	1996	DBLP DOI BibTeX RDF	Risc architecture, frontend compilers, embedded systems
16	Shusuke Okamoto, Masahiro Sowa	Hybrid Processor Based on VLIW and PN-Superscalar.	PDPTA	1996	DBLP BibTeX RDF
16	Kiyoshige Nakamura, Keiichi Sakai, Tadashi Ae	A VLIW Processor For Real-Time Signal Processing.	ISSPA	1996	DBLP DOI BibTeX RDF
16	Andrea Capitanio, Alexandru Nicolau, Nikil D. Dutt	A hypergraph-based model for port allocation on multiple-register-file VLIW architectures.	Int. J. Parallel Program.	1995	DBLP DOI BibTeX RDF
16	Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero	Automatic generation of loop scheduling for VLIW.	PACT	1995	DBLP BibTeX RDF
16	Thomas M. Conte, Sumedh W. Sathaye	Dynamic rescheduling: a technique for object code compatibility in VLIW architectures.	MICRO	1995	DBLP DOI BibTeX RDF
16	James Radigan, Pohua P. Chang, Utpal Banerjee	Integer Loop Code Generation for VLIW.	LCPC	1995	DBLP DOI BibTeX RDF
16	John Lenell, Nader Bagherzadeh	A performance comparison of several superscalar processor models with a VLIW processor.	Microprocess. Microsystems	1994	DBLP DOI BibTeX RDF
16	Marc Pouzet	Fine Grain Parallelisation of Functional Programs for VLIW or Super-scalar Architectures.	Applications in Parallel and Distributed Computing	1994	DBLP BibTeX RDF
16	Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé	Using Sacks to Organize Registers in VLIW Machines.	CONPAR	1994	DBLP DOI BibTeX RDF
16	Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures.	ICPP (1)	1994	DBLP DOI BibTeX RDF
16	Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau	Partitioning of Variables for Multiple-Register-File VLIW Architectures.	ICPP (1)	1994	DBLP DOI BibTeX RDF
16	Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery	The superblock: An effective technique for VLIW and superscalar compilation.	J. Supercomput.	1993	DBLP DOI BibTeX RDF
16	Michael A. Schuette, John Paul Shen	Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer.	J. Supercomput.	1993	DBLP DOI BibTeX RDF
16	Bogong Su, Jian Wang 0046, Zhizhong Tang, Chihong Zhang, Wei Zhao	URPR-1: A single-chip VLIW architecture.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
16	Peter Pfahler, Christof Nagel, Franz-Josef Rammig, Uwe Kastens	Design of a VLIW architecture constructed from standard RISC chips: A case study of hardware/software codesign.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
16	Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale	Addressing mechanisms for VLIW and superscalar processors.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
16	H. Fatih Ugurdag, Christos A. Papachristou	A VLIW architecture based on shifting register files.	MICRO	1993	DBLP DOI BibTeX RDF
16	John Lenell, Nader Bagherzadeh	A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor.	IPPS	1993	DBLP DOI BibTeX RDF
16	David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa	URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
16	Soo-Mook Moon, Kemal Ebcioglu, Ashok K. Agrawala	Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
16	G. Menez, Michel Auguin, Fernand Boéri, C. Carrière	Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
16	Soo-Mook Moon, Kemal Ebcioglu	On Performance, Efficiency of VLIW and Superscalar.	ICPP (2)	1993	DBLP DOI BibTeX RDF
16	C. Carrière, Michel Auguin, Fernand Boéri, G. Menez	A comparison study of minimization methods of unit interconnection in VLIW processors.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
16	Tokuzo Kiyohara, John C. Gyllenhaal	Code scheduling for VLIW/superscalar processors with limited register files.	MICRO	1992	DBLP DOI BibTeX RDF