Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Jürgen Becker 0001, Marcelo O. Johann, Ricardo Reis 0001 (eds.) |
VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Naifeng Jing, Weifeng He, Zhigang Mao |
A general statistical estimation for application mapping in Network-on-Chip. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Levent Aksoy, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001 |
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Brendan Mullane, Vincent O'Brien |
A high performance band-pass DAC architecture and design targeting a low voltage silicon process. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hirokazu Nakazawa, Makoto Ishida, Kazuaki Sawada |
Multimodal proton and fluorescence image sensor for bio applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xin Ming, Ze-kun Zhou, Bo Zhang 0027 |
A low-power ultra-fast capacitor-less LDO with advanced dynamic push-pull techniques. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Siwat Saibua, Liuxi Qian, Dian Zhou |
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Weisheng Zhao, Yue Zhang 0010, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli |
Embedded MRAM for high-speed computing. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xiaohang Wang 0001, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang 0001, Peng Liu 0016 |
Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Alexey Lopich, Piotr Dudek |
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch |
3-D integration and the limits of silicon computation. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo |
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Toshiyuki Tsuchiya, Hiroyuki Tokusaki, Yoshikazu Hirai, Koji Sugano, Osamu Tabata |
Self-dependent equivalent circuit modeling of electrostatic comb transducers for integrated MEMS. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon |
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kiyotaka Sasagawa, Hiroyuki Masuda, Ayato Tagawa, Takuma Kobayashi, Toshihiko Noda, Takashi Tokuda, Jun Ohta |
Micro CMOS image sensor for multi-area imaging. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ernesto Sánchez 0001, Matteo Sonza Reorda, Alberto Paolo Tonda |
On the functional test of Branch Prediction Units based on Branch History Table. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Shaowei Zhen, Bo Zhang 0027, Ping Luo, Kang Yang, Xiaohui Zhu, Jiangkun Li |
A high efficiency synchronous buck converter with adaptive dead time control for dynamic voltage scaling applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ernesto Sánchez 0001, Giovanni Squillero, Alberto Paolo Tonda |
Post-silicon failing-test generation through evolutionary computation. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xiaohui Zhu, Ping Luo, Shaowei Zhen, Kang Yang, Jiangkun Li, Zekun Zhou |
A voltage mode power converter with the function of digitally duty cycle tuning. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Josef Dobes, David Cerný, Abhimanyu Yadav |
A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Le Yu, Haigang Yang, Jia Zhang, Wei Wang 0003 |
Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Pramod Kumar Meher, Sang Yoon Park |
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng |
A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Fernandez Villena, L. Miguel Silveira |
Positive realization of reduced RLCM nets. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jianhua Li 0003, Chun Jason Xue, Yinlong Xu |
STT-RAM based energy-efficiency hybrid cache for CMPs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Franco Fummi, Davide Quaglia, Francesco Stefanni |
Communication-aware middleware-based design-space exploration for Networked Embedded Systems. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ming Zhu, Liyi Xiao, Hong Wei Luo |
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jianfei Jiang 0001, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao |
A clock-less transceiver for global interconnect. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi |
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jeong Hoon Kim, In Jung Lyu, Hyun June Lyu, Jun Rim Choi |
Minimizing redundancy-based motion estimation design for high-definition. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yanan Sun 0003, Volkan Kursun |
Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis |
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Guanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang |
1024-point pipeline FFT processor with pointer FIFOs based on FPGA. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jia Zhang, Le Yu, Haigang Yang, Y. L. Xie, F. B. Zhou, Wei Wang 0003 |
Self-test method and recovery mechanism for high frequency TSV array. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | |
IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011 |
VLSI-SoC |
2011 |
DBLP BibTeX RDF |
|
1 | Charvi Dhoot, Vincent John Mooney, Shubhajit Roy Chowdhury, Lap-Pui Chau |
Fault tolerant design for low power hierarchical search motion estimation algorithms. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Asim Khan, Kyungsu Kang, Chong-Min Kyung |
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Agent-based on-chip network using efficient selection method. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Anupam Chattopadhyay, Zoltan Endre Rakosi |
Combinational logic synthesis for material implication. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Cenni, Serge Scotti, Emmanuel Simeu |
SystemC AMS behavioral modeling of a CMOS video sensor. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Venkata Narasimha Manyam, Dhurv Chhetri, J. Jacob Wikner |
Clockless asynchronous delta modulator based ADC for smart dust applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Seokjoong Kim, Matthew R. Guthaus |
SNM-aware power reduction and reliability improvement in 45nm SRAMs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao |
Robust design of sub-threshold flip-flop cells for wireless sensor network. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Qingyun Ma, Mohammad Rafiqul Haider, Yehia Massoud |
A low-loss rectifier unit for inductive-powering of biomedical implants. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Toshihiko Noda, Takuya Kitao, Takasuke Ito, Kiyotaka Sasagawa, Takashi Tokuda, Yasuo Terasawa, Hiroyuki Tashiro, Hiroyuki Kanda, Takashi Fujikado, Jun Ohta |
Fabrication of a flexible neural interface device with CMOS-based smart electrodes. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo |
Area-efficient 3-input decimal adders using simplified carry and sum vectors. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Tzu-Chi Huang, Yao-Yi Yang, Yu-Huei Lee, Ming-Jhe Du, Shih-Hsien Cheng, Ke-Horng Chen |
A battery-free energy harvesting system with the switch capacitor sampler (SCS) technique for high power factor in smart meter applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Zhijian Zhou, Man Wong, Libor Rufer |
Wide-band piezoresistive aero-acoustic microphone. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Janet Meiling Wang Roveda, Susan Lysecky, Young-Jun Son, Hyungtaek Chang, Anita Annamalai, Xiao Qin 0002 |
Interface model based cyber-physical energy system design for smart grid. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Khawar Sarfraz |
A novel low-leakage 8T differential SRAM cell. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jing Xie 0010, Huimin Xing, Zhigang Mao |
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Roman Plyaskin, Andreas Herkersdorf |
Context-aware compiled simulation of out-of-order processor behavior based on atomic traces. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor |
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | J. Gerardo García-Sánchez, José M. de la Rosa 0001 |
Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecom. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | H. Gregor Molter, André Seffrin, Sorin A. Huss |
State space optimization within the DEVS model of computation for timing efficiency. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Alex Man Ho Kwan, Sichao Song, Xing Lu, Lei Lu, Ying-Khai Teh, Ying Fei Teh, Eddie Wing Cheung Chong, Yan Gao, William Hau, Fan Zeng, Man Wong, Chunmei Huang, Akira Taniyama, Yoshihide Makino, So Nishino, Toshiyuki Tsuchiya, Osamu Tabata |
Designs for improving the performance of an electro-thermal in-plane actuator. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng |
MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Felipe Frantz, Lioua Labrak, Ian O'Connor |
3D-IC floorplanning: Applying meta-optimization to improve performance. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hong-Yuan Jheng, Yen-Hsiang Chen, Shanq-Jang Ruan, Ziming Qi |
FPGA implementation of high sampling rate in-car non-stationary noise cancellation based on adaptive Wiener filter. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev |
Communication centric on-chip power grid models for networks-on-chip. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Keisuke Inoue, Mineo Kaneko |
Early planning for RT-level delay insertion during clock skew-aware register binding. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Huan Chen 0001, João Marques-Silva 0001 |
Improvements to satisfiability-based boolean function bi-decomposition. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos |
Prospects of 3D inductors on through silicon vias processes for 3D ICs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Manas Kumar Puthal, Virendra Singh, Manoj Singh Gaur, Vijay Laxmi |
C-Routing: An adaptive hierarchical NoC routing methodology. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui |
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui |
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Pascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy |
3D NoC using through silicon Via: An asynchronous implementation. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xiaojin Zhao, Amine Bermak, Farid Boussaïd |
A low cost CMOS polarimetric ophthalmoscope scheme for cerebral malaria diagnostics. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao |
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jizeng Wei, Yisong Chang, Wei Guo 0005, Jizhou Sun |
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Joseph Sankman, Dongsheng Ma 0001 |
A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu |
Network-on-Chip multicasting with low latency path setup. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon |
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Haotian Liu, Fengrui Shi, Yuanzhe Wang, Ngai Wong |
Frequency-domain transient analysis of multitime partial differential equation systems. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu |
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC). |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang 0041, Philip C. H. Chan |
Towards future VLSI interconnects using aligned carbon nanotubes. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Marcel Veloso Campos, André Luís Fortunato, Carlos Alberto dos Reis Filho |
New 12-bit source-follower track-and-hold circuit suitable for high-speed applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wing-Hung Ki, Yan Lu 0002, Feng Su, Chi-Ying Tsui |
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi |
An easily testable routing architecture of FPGA. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar |
Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Pramod Kumar Meher, Yu Pan |
MCM-based implementation of block FIR filters for high-speed and low-power applications. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Amit Berman, Ran Ginosar, Idit Keidar |
Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Somsubhra Talapatra, Hafizur Rahaman 0001 |
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm). |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Abdulkadir Akin, Mert Cetin, Burak Erbagci, Ozgur Karakaya, Ilker Hamzaoglu |
An adaptive bilateral motion estimation algorithm and its hardware architecture. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yngvar Berg |
Novel ultra low-voltage and high speed domino CMOS logic. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jimson Mathew, Savita Banerjee, Hafizur Rahaman 0001, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir |
On the synthesis of attack tolerant cryptographic hardware. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Seunghan Lee, Kyungsu Kang, Chong-Min Kyung |
Temperature- and bus traffic- aware data placement in 3D-stacked cache. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Joachim Neves Rodrigues, Omer Can Akgun, Viktor Öwall |
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Niccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi |
A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine |
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jongpil Jung, Seonpil Kim, Chong-Min Kyung |
Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Eliyah Kilada, Shomit Das, Kenneth S. Stevens |
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni |
Reduction of process variation effect on FPGAs using multiple configurations. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk |
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Hailong Jiao, Volkan Kursun |
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marc Pons 0001, Francesc Moll, Antonio Rubio 0001, Jaume Abella 0001, Xavier Vera, Antonio González 0001 |
VCTA: A Via-Configurable Transistor Array regular fabric. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Diego Jaccottet, Eduardo Costa 0001, Levent Aksoy, Paulo F. Flores, José Monteiro 0001 |
Design of low-complexity and high-speed digital Finite Impulse Response filters. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Michele Magno, Alessandro Lanza, Davide Brunelli, Luigi Di Stefano, Luca Benini |
Energy aware multimodal embedded video surveillance. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mojtaba Valinataj, Siamak Mohammadi |
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Pramod Kumar Meher |
Novel input coding technique for high-precision LUT-based multiplication for DSP applications. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|