Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Arnab Sarkar, Arijit Mondal |
Partitioned Fair Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded Systems. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta |
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | M. V. Prajwal, B. S. Srinivas, S. Shodhan, M. K. Jayaram Reddy, Tonse Laxminidhi |
A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal |
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa |
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman 0001 |
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma |
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Debiprasanna Sahoo, Manoranjan Satpathy |
MSimDRAM: Formal Model Driven Development of a DRAM Simulator. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mark M. Tehranipoor |
New Directions in Hardware Security. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Tanya Shreedhar, Sujay Deb |
Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Wazir Singh, Sujay Deb |
Energy Efficient and Congestion-Aware Router Design for Future NoCs. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sudhi Proch, Prabhat Mishra 0001 |
Test Generation for Hybrid Systems Using Clustering and Learning Techniques. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar 0001, Akash Pacharne, H. Narayanan, Sachin B. Patkar |
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan |
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi |
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan |
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vinaya M. M., Roy Paily, Anil Mahanta |
Power Optimization of LNA for LTE Receiver. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ritsuko Muguruma, Shigeru Yamashita |
Stochastic Number Generation with Few Inputs. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Apoorva Pathak, Divyesh Sachan, Harish Peta, Manish Goswami |
A Modified SRAM Based Low Power Memory Design. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Richa Mishra, Tarun Kanti Bhattacharyya, Tapas Kumar Maiti |
Design and Simulation of Microfluidic Components towards Development of a Controlled Drug Delivery Platform. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Arindam Banerjee 0003, Debesh Kumar Das |
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abhishek Chakraborty 0001, Debdeep Mukhopadhyay |
A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ingrid Verbauwhede, Debdeep Mukhopadhyay, Sujoy Sinha Roy |
Embedded Security. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta |
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shankarayya G. Kambalimath, Prem C. Pandey 0001, Pandurangarao N. Kulkarni, Shivaling S. Mahant-Shetti, Sangamesh G. Hiremath |
FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio Input. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita |
ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Rajit Karmakar, Santanu Chattopadhyay |
Thermal-Safe Schedule Generation for System-on-Chip Testing. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | M. Mohamed Asan Basiri, S. K. Noor Mahammad |
An Efficient VLSI Architecture for Discrete Hadamard Transform. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani |
The Future of NoCs: New Technologies and Architectures. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jos A. V. Prakash, Babita R. Jose, Jimson Mathew |
A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta Modulator. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Susanta Sengupta |
RF System Design of an RFIC Receiver for IoT. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Debashish Sahu, Siddhartha Hazra, Prajit Nandi |
Modeling of Linear Variable Differential Transformer. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha |
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger |
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra |
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shirshendu Das, Hemangee K. Kapoor |
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mahendra Sakare |
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee |
TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy 0001 |
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Swagath Venkataramani, Kaushik Roy 0001, Anand Raghunathan |
Approximate Computing. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | William Lee, Tannu Sharma, Kenneth S. Stevens |
Path Based Timing Validation for Timed Asynchronous Design. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Kamlesh Singh, Shanthi Pavan |
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Adit D. Singh |
Adaptive Test Methods for High IC Quality and Reliability. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Saurabh R. Anmadwar, Nandakumar Nambath, Shalabh Gupta |
Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu |
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao |
A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Saroj Mondal, Roy P. Paily |
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Nilanjan Mukherjee 0001, Janusz Rajski |
Digital Testing of ICs for Automotive Applications. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Muralidharan Venkatasubramanian, Vishwani D. Agrawal |
Database Search and ATPG - Interdisciplinary Domains and Algorithms. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vineeta Shukla, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Nor Hisham Hamid, Madiha A. Sheikh |
Fault Modeling and Simulation of MEDA Based Digital Microfluidics Biochips. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Samiran Dam, Pradip Mandal |
A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Rahul Shrestha, Utkarsh Rastogiy |
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Lawrence M. Schlitt, Priyank Kalla, Steve Blair |
A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | |
29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016 |
VLSID |
2016 |
DBLP BibTeX RDF |
|
1 | Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy 0001, Ranjani Narayan |
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Rakesh Prasher, Devi Dass, Rakesh Vaid |
Al/HfO2/Si Gate Stack with Improved Physical and Electrical Parameters. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak |
Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri |
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abishek Thekkeyil Kunnath, Bibhudatta Sahoo 0002 |
A Digitally Assisted Radiation Hardened Current Steering DAC. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sandeep K. Shukla |
Cyber Security of Cyber Physical Systems: Cyber Threats and Defense of Critical Infrastructures. |
VLSID |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Chandrashekar Dusa, Samiyuktha Kalalii, Pachamuthu Rajalakshmi, Omkeshwar Rao |
Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar 0001, S. Gurunarayanan 0001 |
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Felipe Lavratti, LetÃcia Maria Bolzani Poehls, Fabian Vargas 0001, Andrea Calimera, Enrico Macii |
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | B. N. Bhramar Ray, Shankar Balachandran |
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Saurabh Kumar Singh, Nitin Bansal |
Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sai Praveen Kadiyala, Debasis Samanta |
On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Satya Narayan Shukla, Karan Kakwani, Amit Patra, Bipin Kumar Lahkar, Vivek Kumar Gupta, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth |
Noninvasive Cuffless Blood Pressure Measurement by Vascular Transit Time. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jude Angelo Ambrose, Tuo Li 0001, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran |
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hadi Hajimiri, Kamran Rahmani, Prabhat Mishra 0001 |
Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jude Baby George, Grace Mathew Abraham, Bharadwaj Amrutur, Sujit Kumar Sikdar |
Robot Navigation Using Neuro-electronic Hybrid Systems. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sajib Kumar Mitra, Ahsan Raja Chowdhury |
Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Kirmender Singh, A. B. Bhattacharyya |
Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Suman Chatterjee, Vikram Singh Saun, Anand Arunachalam 0001 |
A Methodology for Placement of Regular and Structured Circuits. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Saurav Kumar Ghosh, Aritra Hazra, Soumyajit Dey |
RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Parmesh Ramanathan |
Tutorial T8: Scheduling Issues in Embedded Real-Time Systems. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jacob A. Abraham, Abhijit Chatterjee |
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Radhika Gupta, Atul Bhargava, Rakeshshenoy Panemangalore |
Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Anjan Kumar, Abhinav Dikshit, Bill Clark, Jeff Yan |
A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sameer Pawanekar, Gaurav Trivedi, Kalpesh Kapoor |
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala |
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover |
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski |
CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sriram Ganesan |
Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Virendra Gupta, Jayaraghavendran |
Invited Talk: IoT Protocols War and the Way Forward. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nitin S. Kale |
Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and Biosensors. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sumana Ghosh, Pallab Dasgupta |
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Pravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani, C. K. Ramesha |
Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Prabhat Mishra 0001, Swarup Bhunia, Srivaths Ravi 0001 |
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani |
FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin |
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shirshendu Das, Hemangee K. Kapoor |
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Abhishek Jain 0003, Richa Gupta |
Scaling the UVM_REG Model towards Automation and Simplicity of Use. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja |
Thermal Extension of the Total Bandwidth Server. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Debesh Bhatta, Suvadeep Banerjee, Abhijit Chatterjee |
A Noise Aware CML Latch Modelling for Large System Simulation. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Unsuk Heo, Xueqing Li, Huichu Liu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan |
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Pratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman 0001 |
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Vikas Kaushal, Bharat Garg, Ankur Jaiswal, G. K. Sharma 0001 |
Energy Aware Computation Driven Approximate DCT Architecture for Image Processing. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Cory E. Merkel, Dhireesha Kudithipudi |
Comparison of Off-Chip Training Methods for Neuromemristive Systems. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Partha Pratim Saha, Sumonto Saha, Tuhina Samanta |
Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
1 | T. V. Prabhakar 0001, Ujwal Mysore, Uday Saini, K. J. Vinoy, Bharadwaj Amruthur |
NFC for Pervasive Healthcare Monitoring. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|