Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Kyung-Ju Cho, Suhyun Jo, Yong-Eun Kim, Yi-Nan Xu, Jin-Gyun Chung	Constant multiplier design using specialized bit pattern adders.	ICECS	2008	DBLP DOI BibTeX RDF
16	Taeko Matsunaga, Yusuke Matsunaga	Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
16	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
16	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	Low energy 16-bit Booth leapfrog array multiplier using dynamic adders.	IET Circuits Devices Syst.	2007	DBLP DOI BibTeX RDF
16	Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López	Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
16	Chiu-Wah Ng, Ngai Wong, Tung-Sang Ng	Bit-Stream Adders and Multipliers for Tri-Level Sigma-Delta Modulators.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
16	Jon Alfredsson, Snorre Aunet	Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.	PATMOS	2007	DBLP DOI BibTeX RDF
16	Fekri Kharbash, Ghulam M. Chaudhry	The performance of parallel prefix adders on nanometer FPGA.	PDCS	2007	DBLP BibTeX RDF
16	Massimo Alioto, Gaetano Palumbo	Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders.	ECCTD	2007	DBLP DOI BibTeX RDF
16	J. J. Rodriguez-Navarro	Comments on "Carry checking/parity prediction adders and ALUs".	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
16	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
16	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format	CoRR	2006	DBLP BibTeX RDF
16	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format	CoRR	2006	DBLP BibTeX RDF
16	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.	ETS	2006	DBLP DOI BibTeX RDF
16	Bijoy Antony Jose, Damu Radhakrishnan	Delay Optimized Redundant Binary Adders.	ICECS	2006	DBLP DOI BibTeX RDF
16	Massimo Alioto, Gaetano Palumbo	Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.	ICECS	2006	DBLP DOI BibTeX RDF
16	Massimo Alioto, Gaetano Palumbo	Delay uncertainty due to supply variations in static and dynamic full adders.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Localization of Faults in Radix-n Signed Digit Adders.	IOLTS	2006	DBLP DOI BibTeX RDF
16	Yanjie Mao, Chunhong Chen	Performance Evaluation and Optimization of Full Adders with Single-Electron Technology.	CCECE	2006	DBLP DOI BibTeX RDF
16	Debatosh Debnath, Tsutomu Sasao	Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
16	Pasquale Corsonello, Stefania Perri	Efficient Reconfigurable Manchester Adders for Low-power Media Processing.	J. Circuits Syst. Comput.	2005	DBLP DOI BibTeX RDF
16	Haridimos T. Vergos, Costas Efstathiou	On the Design of Efficient Modular Adders.	J. Circuits Syst. Comput.	2005	DBLP DOI BibTeX RDF
16	Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	New architectures for modulo 2N - 1 adders.	ICECS	2005	DBLP DOI BibTeX RDF
16	Andrew G. Dempster, Malcolm D. Macleod	Multiplication by two integers using the minimum number of adders.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
16	Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang	The CMOS carry-forward adders.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre	Power-delay product minimization in high-performance 64-bit carry-select adders.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
16	Ilya Obridko, Ran Ginosar	Low energy asynchronous adders.	ICECS	2004	DBLP DOI BibTeX RDF
16	Elizabeth J. Brauer, Yusuf Leblebici	Low noise MCML prefix adders using 0.18 µm CMOS technology.	Circuits, Signals, and Systems	2004	DBLP BibTeX RDF
16	Henrik Eriksson, Per Larsson-Edefors	Dynamic pass-transistor dot operators for efficient parallel-prefix adders.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar	Multiplier blocks using carry-save adders.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Massimo Alioto, Gaetano Palumbo, Massimo Poli	A gate-level strategy to design Carry Select Adders.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Pasquale Corsonello, Stefania Perri, Vitit Kantabutra	Area- and Power-Reduced Standard-Cell Spanning Tree Adders.	ESA/VLSI	2004	DBLP BibTeX RDF
16	José Fernández Ramos, Javier López García, Santiago Cárdenas Martín, Alfonso Gago Bohórquez	A new theorem in threshold logic and its application to multioperand binary adders.	Int. J. Comput. Math.	2003	DBLP DOI BibTeX RDF
16	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
16	Radu Zlatanovici, Borivoje Nikolic	Power-performance optimal 64-bit carry-lookahead adders.	ESSCIRC	2003	DBLP DOI BibTeX RDF
16	B. Kiran Kumar, Parag K. Lala	On-line Detection of Faults in Carry-Select Adders.	ITC	2003	DBLP DOI BibTeX RDF
16	Chien-In Henry Chen, Mahesh Wagh	Testability Synthesis for Jumping Carry Adders.	VLSI Design	2002	DBLP DOI BibTeX RDF
16	Johnnie A. Huang, Chien-In Henry Chen	Timing-Driven-Testable Convergent Tree Adders.	VLSI Design	2002	DBLP DOI BibTeX RDF
16	Hoang Q. Dao, Vojin G. Oklobdzija	Performance Comparison of VLSI Adders Using Logical Effort.	PATMOS	2002	DBLP DOI BibTeX RDF
16	Ioannis Kouretas, Vassilis Paliouras	High-radix modulo rn - 1 multipliers and adders.	ICECS	2002	DBLP DOI BibTeX RDF
16	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Ling adders in CMOS standard cell technologies.	ICECS	2002	DBLP DOI BibTeX RDF
16	Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello	Speed-efficient wide adders for VIRTEX FPGAs.	ICECS	2002	DBLP DOI BibTeX RDF
16	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	Low-voltage asynchronous adders for low power and high speed applications.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
16	Leyla Nazhandali, Karem A. Sakallah	Majority-Based Decomposition of Carry Logic in Binary Adders.	IWLS	2002	DBLP BibTeX RDF
16	Junhyung Um, Taewhan Kim	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	VLSI, arithmetic circuits, Carry-save-addition
16	Youngtae Kim, Taewhan Kim	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.	ASP-DAC	2001	DBLP DOI BibTeX RDF
16	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	On the design of modulo 2n±1 adders.	ICECS	2001	DBLP DOI BibTeX RDF
16	Dimitrios Soudris, Vasilis F. Pavlidis, Adonios Thanailakis	Designing low-power energy recovery adders based on pass transistor logic.	ICECS	2001	DBLP DOI BibTeX RDF
16	Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek	Design Alternatives for Parallel Saturating Multioperand Adders.	ICCD	2001	DBLP DOI BibTeX RDF
16	Hyeong-Ju Kang, In-Cheol Park	Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
16	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
16	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.	LATW	2001	DBLP BibTeX RDF
16	Zhan Yu, Meng-Lin Yu, Alan N. Willson Jr.	Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits.	DAC	2001	DBLP DOI BibTeX RDF
16	Gustavo A. Ruiz	Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits".	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
16	Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser	Threshold logic circuit design of parallel adders using resonant tunneling devices.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
16	Youngtae Kim, Taewhan Kim	An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.	J. Circuits Syst. Comput.	2000	DBLP DOI BibTeX RDF
16	Taewhan Kim, Junhyung Um	A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
16	Taewhan Kim, Junhyung Um	A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).	ASP-DAC	2000	DBLP DOI BibTeX RDF
16	Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park	FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Michael J. Schulte, Pablo I. Balzola, Jie Ruan, C. John Glossner	Parallel saturating multioperand adders.	CASES	2000	DBLP DOI BibTeX RDF
16	Zhen Luo, Ruby B. Lee	Cost-effective multiplication with enhanced adders for multimedia applications.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Jiun-In Guo	An efficient design for one dimensional discrete cosine transform using parallel adders.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Mihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths.	LATW	2000	DBLP BibTeX RDF
16	Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga	Adders.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
16	Junhyung Um, Taewhan Kim, C. L. Liu 0001	Optimal allocation of carry-save-adders in arithmetic optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
16	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
16	Gustavo A. Ruiz	Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
16	Javier D. Bruguera, Tomás Lang	Leading-one prediction scheme for latency improvement in single datapath floating-point adders.	ICCD	1998	DBLP DOI BibTeX RDF
16	Taewhan Kim, William Jao, Steven W. K. Tjiang	Arithmetic Optimization Using Carry-Save-Adders.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
16	Zhongde Wang, Graham A. Jullien, William C. Miller, Jinghong Wang, Sami S. Bizzan	Fast adders using enhanced multiple-output domino logic.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	Bernd Rederlechner, Jörg Keller 0001	A Note on Correctness Proofs for Overflow Detection Logic in Adders for d-th Complement Numbers.	J. Univers. Comput. Sci.	1997	DBLP DOI BibTeX RDF
16	Bernard Laurent, Gilles Bosco, Gabriele Saucier	Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA.	FPL	1997	DBLP DOI BibTeX RDF
16	Abdellatif Bellaouar, H. Touzene	3.3-V BiCMOS current-mode logic circuits for high-speed adders.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
16	Alessandro De Gloria, Mauro Olivieri	Statistical Carry Lookahead Adders.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
16	Paul F. Stelling, Vojin G. Oklobdzija	Design strategies for optimal hybrid final adders in a parallel multiplier.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
16	Michael J. Batek, John P. Hayes	Optimal Testing and Design of Adders.	VLSI Design	1994	DBLP DOI BibTeX RDF
16	Mark A. Franklin, Tienyo Pan	Performance comparison of asynchronous adders.	ASYNC	1994	DBLP DOI BibTeX RDF
16	A. Kazeminejad, Keivan Navi, Daniel Etiemble	CML Current Mode Full Adders for 2.5-V Power Supply.	ISMVL	1994	DBLP DOI BibTeX RDF
16	Keivan Navi, A. Kazeminejad, Daniel Etiemble	Performance of CMOS Current Mode Full Adders.	ISMVL	1994	DBLP DOI BibTeX RDF
16	Hans Lindkvist, Per Andersson	Techniques for Fast CMOS-based Conditional Sum Adders.	ICCD	1994	DBLP DOI BibTeX RDF
16	June Wang, Zhongde Wang, Graham A. Jullien, William C. Miller	Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic.	ISCAS	1994	DBLP DOI BibTeX RDF
16	Yuang-Ming Hsu, Earl E. Swartzlander Jr.	Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers.	DFT	1994	DBLP BibTeX RDF
16	Zhan Chen, Israel Koren	A Yield Study of VLSI Adders.	DFT	1994	DBLP BibTeX RDF
16	Janusz Rajski, Jerzy Tyszer	Test responses compaction in accumulators with rotate carry adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
16	Michael Nicolaidis	Efficient Implementations of Self-Checking Adders and ALUs.	FTCS	1993	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Rolf Drechsler, Paul Molitor	On the implementation of an efficient performance driven generator for conditional-sum-adders.	EURO-DAC	1993	DBLP DOI BibTeX RDF
16	Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.	A Comparative Evaluation of Adders Based on Performance and Testability.	ICCD	1993	DBLP DOI BibTeX RDF
16	Zhongde Wang, Graham A. Jullien, William C. Miller, June Wang	New Concepts for the Design of Carry Lookahaead Adders.	ISCAS	1993	DBLP BibTeX RDF
16	Clark D. Thomborson, Yi Sun	Optimizing carry lookahead adders for semicustom CMOS.	Great Lakes Symposium on VLSI	1993	DBLP DOI BibTeX RDF
16	Yuang-Ming Hsu, Earl E. Swartzlander Jr.	VLSI Concurrent Error Correcting Adders and Multipliers.	DFT	1993	DBLP BibTeX RDF
16	Uwe Sparmann	On the check base selection problem for fast adders.	VTS	1993	DBLP DOI BibTeX RDF
16	Juan J. Ramirez, Kenneth R. Prestwich, Ian D. Smith	High-power, short-pulse generators based on induction voltage adders.	Proc. IEEE	1992	DBLP DOI BibTeX RDF
16	Eberhard Zehendner	Efficient implementation of regular parallel adders for binary signed digit number representations.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Paul Molitor	A performance driven generator for efficient testable conditional-sum-adders.	EURO-DAC	1992	DBLP DOI BibTeX RDF
16	Lutz J. Micheel	Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and Multipliers.	ISMVL	1992	DBLP DOI BibTeX RDF
16	Gopal Lakhani	VLSI Design of Modulo Adders/Subtractors.	ICCD	1992	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Uwe Sparmann	A uniform test approach for RCC-adders.	Fundam. Informaticae	1991	DBLP BibTeX RDF
16	Ferruccio Barsi, Enrico Martinelli	A VLSI architecture for RNS with MI adders.	Integr.	1991	DBLP DOI BibTeX RDF
16	Carlos Delgado Kloos, Walter Dosch	Transformational Development of Circuit Descriptions for Binary Adders.	Methods of Programming	1991	DBLP DOI BibTeX RDF