Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Amir Zjajo, José Pineda de Gyvez	Calibration and Debugging of Multi-step Analog to Digital Converters.	DELTA	2008	DBLP DOI BibTeX RDF	multi-step ADC, debugging, calibration, design-for-test
17	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples.	VLSI Design	2008	DBLP DOI BibTeX RDF
17	Shanthi Pavan, Nagendra Krishnapura	Oversampling Analog-to-Digital Converter Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
17	Yalin Evren Sagduyu, Dongning Guo, Randall Berry	On the delay and throughput of digital and analog network coding for wireless broadcast.	CISS	2008	DBLP DOI BibTeX RDF
17	Abhishek Somani, P. P. Chakrabarti 0001, Amit Patra	An Evolutionary Algorithm-Based Approach to Automated Design of Analog and RF Circuits Using Adaptive Normalized Cost Functions.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
17	Rashid Rashidzadeh, Majid Ahmadi, William C. Miller	Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	Giuseppe Caire, Krishna R. Narayanan	On the Distortion SNR Exponent of Hybrid Digital-Analog Space-Time Coding.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
17	Angan Das, Ranga Vemuri	An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms.	ISVLSI	2007	DBLP DOI BibTeX RDF
17	Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell	Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.	ISVLSI	2007	DBLP DOI BibTeX RDF
17	Almitra Pradhan, Ranga Vemuri	Regression based circuit matrix models for accurate performance estimation of analog circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
17	Daniel Mueller 0001, Helmut E. Graeb, Ulf Schlichtmann	Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.	DATE	2007	DBLP DOI BibTeX RDF
17	John Lataire, Gerd Vandersteen, Rik Pintelon	Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations.	DATE	2007	DBLP DOI BibTeX RDF
17	Il Song Han	Membership Function Circuit for Neural/Fuzzy Hardware of Analog-Mixed Operation Based on the Programmable Conductance.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
17	David Walter, Scott Little, Chris J. Myers	Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver.	ATVA	2007	DBLP DOI BibTeX RDF
17	Cheol-Sun Park, Dae Young Kim 0001	Modulation Classification of Analog and Digital Signals Using Neural Network and Support Vector Machine.	ISNN (3)	2007	DBLP DOI BibTeX RDF
17	Joachim Becker, Stanis Trendelenburg, Fabian Henrici, Yiannos Manoli	Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm.	GECCO	2007	DBLP DOI BibTeX RDF	hardware realization, genetic algorithm, computer aided design, synthesis, evolvable hardware, microelectronics
17	Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti	A distortion model for pipeline Analog-to-Digital converters.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Angan Das, Ranga Vemuri	GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Josep Soler Garrido, Robert J. Piechocki	Analog Implementation of a Mean Field Detector for Multiple Antenna Systems.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Henry H. Y. Chan, Zeljko Zilic	A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Dongwon Seo, Yuhua Guo, Manu Mishra	High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices only.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Fule Li, Zhihua Wang 0001, Dongmei Li	An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Peter R. Kinget	Device Mismatch: An Analog Design Perspective.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon	A Current-Mode Analog Circuit for Reinforcement Learning Problems.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Andreas Tritschler	A Continuous Time Analog-to-Digital Converter With 90µW and 1.8µV/LSB Based on Differential Ring Oscillator Structures.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Christopher S. Taillefer, Gordon W. Roberts	Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Jason N. Laska, Sami Kirolos, Marco F. Duarte, Tamer Ragheb, Richard G. Baraniuk, Yehia Massoud	Theory and Implementation of an Analog-to-Information Converter using Random Demodulation.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert	Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.	DAC	2007	DBLP DOI BibTeX RDF
17	Jian Wang, Xin Li 0001, Lawrence T. Pileggi	Parameterized Macromodeling for Analog System-Level Design Exploration.	DAC	2007	DBLP DOI BibTeX RDF
17	Mohammad Maymandi-Nejad, Manoj Sachdev	DTMOS Technique for Low-Voltage Analog Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
17	Fang Liu 0029, Sule Ozev, Martin A. Brooke	Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Hua Tang, Hui Zhang 0057, Alex Doboli	Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Lihong Zhang, Rabin Raut, Yingtao Jiang, Ulrich Kleine	Placement Algorithm in Analog-Layout Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Trent McConaghy, Georges G. E. Gielen	Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns.	DATE	2006	DBLP DOI BibTeX RDF
17	Huiying Yang, Ranga Vemuri	Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis.	DATE	2006	DBLP DOI BibTeX RDF
17	Michael A. Terry, Jonathan Marcus, Matthew Farrell, Varun Aggarwal, Una-May O'Reilly	GRACE: Generative Robust Analog Circuit Exploration.	EvoWorkshops	2006	DBLP DOI BibTeX RDF
17	Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda	Verification of analog/mixed-signal circuits using labeled hybrid petri nets.	ICCAD	2006	DBLP DOI BibTeX RDF	hybrid petri nets, formal methods
17	Geoffrey A. Hollinger, David A. Gwaltney	Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot.	GECCO	2006	DBLP DOI BibTeX RDF	inspection robots, genetic algorithms, robot control, evolvable hardware, piezoelectric actuators
17	Ying Wei 0002, Alex Doboli	Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Karel Zaplatilek, Karel Hajek	Time domain analysis of analog filters in MATLAB environment.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Jaewook Kim, SeongHwan Cho	A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Charles E. Stroud, Dayu Yang, Foster F. Dai	Analog frequency response measurement in mixed-signal systems.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Christian Vogel 0001, Håkan Johansson	Time-interleaved analog-to-digital converters: status and future directions.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Matthieu Arzel, Fabrice Seguin, Cyril Lahuec, Michel Jézéquel	Semi-iterative analog turbo decoding.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Daniel Mueller 0001, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann	Fast evaluation of analog circuit structures by polytopal approximations.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Mukesh Ranjan, Ranga Vemuri	Exact hierarchical symbolic analysis of large analog networks using a general interconnection template.	ISCAS	2006	DBLP DOI BibTeX RDF
17	D. S. Karadimas, D. N. Mavridis, K. A. Efstathiou	A digitally calibrated R-2R ladder architecture for high performance digital-to-analog converters.	ISCAS	2006	DBLP DOI BibTeX RDF
17	R. Jancke, P. Schwarz	Supporting analog synthesis by abstracting circuit behavior using a modeling methodology.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Munkyo Seo, Mark J. W. Rodwell, Upamanyu Madhow	Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: experimental verification.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Eric E. Fabris, Luigi Carro, Sergio Bampi	Reconfigurable analog interface for mixed signal SOC.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Andrei Vladimirescu, Radu Zlatanovici, Paul G. A. Jespers	Analog circuit synthesis using standard EDA tools.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Seogheon Ham, Yonghee Lee, Wunki Jung, Seunghyun Lim, Kwisung Yoo, Youngcheol Chae, Jihyun Cho, Dongmyung Lee, Gunhee Han	CMOS image sensor with analog gamma correction using nonlinear single-slope ADC.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Josep Altet, Diego Mateo, José Luis González 0001, Eduardo Aldrete-Vidrio	Observation of high-frequency analog/RF electrical circuit characteristics by on-chip thermal measurements.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Mohammad B. Vahidfar, Omid Shoaei, M. Fardis	A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai	Behavioral macromodeling of analog LSI implementation for automobile intake system.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Rajeshuni Ramesham, Joseph Neff, Srinivas Katkoori	Temperature-Adaptive Circuits on Reconfigurable Analog Arrays.	AHS	2006	DBLP DOI BibTeX RDF
17	Mustafa Keskin	A Background Mismatch Calibration For Capacitive Digitial-To-Analog Converters RTERS.	AHS	2006	DBLP DOI BibTeX RDF
17	Mohamed H. Zaki, Sofiène Tahar, Guy Bois	A practical approach for monitoring analog circuits.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
17	Rasit Onur Topaloglu	Monte Carlo-Alternative Probabilistic Simulations for Analog Systems.	ISQED	2006	DBLP DOI BibTeX RDF
17	Alex J. Cannon	A Hybrid Neural Network/Analog Model for Climate Downscaling.	IJCNN	2006	DBLP DOI BibTeX RDF
17	Amlan Ghosh, Abhishek Ranjan, Nirmal B. Chakrabarti	Design and Implementation of Analog Multitone Signal Generator Using Regenerative Frequency Divider for OFDM Transceiver.	DELTA	2006	DBLP DOI BibTeX RDF
17	M. S. Bhat 0001, S. Rekha, H. S. Jamadagni	Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
17	K. Narasimhulu, V. Ramgopal Rao	Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies.	VLSI Design	2006	DBLP DOI BibTeX RDF
17	Zhangcai Huang, Yasuaki Inoue, Hong Yu 0013, Quan Zhang	A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.	APCCAS	2006	DBLP DOI BibTeX RDF
17	Tim Kaulmann, Markus Ferber, Ulf Witkowski, Ulrich Rückert 0001	Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks.	IWANN	2005	DBLP DOI BibTeX RDF
17	Daniel Hostetler, Yuan Xie 0001	Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters.	ISVLSI	2005	DBLP DOI BibTeX RDF
17	Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen	CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.	DATE	2005	DBLP DOI BibTeX RDF
17	Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra	Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits.	DATE	2005	DBLP DOI BibTeX RDF
17	Raoul F. Badaoui, Ranga Vemuri	Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis.	DATE	2005	DBLP DOI BibTeX RDF
17	Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho	Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits.	DATE	2005	DBLP DOI BibTeX RDF
17	Jacques-Olivier Klein, Lionel Lacassagne, Hervé Mathias, Sebastien Moutault, Antoine Dupret	Low Power Image Processing: Analog Versus Digital Comparison.	CAMP	2005	DBLP DOI BibTeX RDF
17	Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu 0001, Lei He 0001	Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang	Placement with symmetry constraints for analog layout design using TCG-S.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Donald Y. C. Lie	What Comes After Most Semiconductor Fabs Are "OutSourced" to Asia? Major Challenges in Educating Future RF/Analog IC Designers in the U.S..	MSE	2005	DBLP DOI BibTeX RDF
17	Yadong Wang, Fady Alajaji, Tamás Linder	Design of VQ-Based Hybrid Digital-Analog Joint Source-Channel Codes for Image Communication.	DCC	2005	DBLP DOI BibTeX RDF
17	Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel	Digital built-in self-test of CMOS analog iterative decoders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Oscar E. Agazzi, Venu Gopinathan	Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniques.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
17	Peter R. Kinget, Aurel A. Lazar, László T. Tóth	On the robustness of an analog VLSI implementation of a time encoding machine.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
17	Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel	. Analog slice turbo decoding.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
17	Sunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo	A 0.9-V 67-µW analog front-end using adaptive-SNR technique for digital hearing aid.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
17	Peng Wang, Shiyuan Yang	Soft fault test and diagnosis for analog circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Hui Zhang 0057, Preethi Karthik, Hua Tang, Alex Doboli	An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
17	Benny Sallberg, Mattias Dahl, Henrik Åkesson, Ingvar Claesson	A mixed analog-digital hybrid for speech enhancement purposes.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
17	Qingyan Liu, Chika O. Nwankpa	Applications of operational transconductance amplifier in power system analog emulation.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
17	Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen	A new CCII-based pipelined analog to digital converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
17	Vlatko Becanovic, Stefan Kubina, Alan A. Stocker	An embedded vision system based on an analog VLSI vision sensor [robot vision applications].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Erhan Ozalevli, Christopher M. Twigg, Paul E. Hasler	10-bit programmable voltage-output digital-analog converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
17	Mehdi Jafaripanah, Bashir M. Al-Hashimi, Neil M. White	Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications].	ISCAS (6)	2005	DBLP DOI BibTeX RDF
17	Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi 0001, Hiroshi Sakayori	A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
17	Laura Vesalainen, Jonne Poikonen, Ari Paasio	A Gray-coded digital-to-analog converter for a mixed-mode processor array.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
17	Zhihao Xu, Dongming Jin, Zhijian Li	Design of an Analog Adaptive Fuzzy Logic Controller.	FSKD (1)	2005	DBLP DOI BibTeX RDF
17	Jihyun Lee, Yong-Bin Kim	ASLIC: A Low Power CMOS Analog Circuit Design Automation.	ISQED	2005	DBLP DOI BibTeX RDF
17	Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.	VTS	2005	DBLP DOI BibTeX RDF	FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
17	Edward Ramsden, Garrison W. Greenwood, David Hunter	EARP-1 - An Evolvable Analog Research Platform.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
17	David A. Gwaltney, Michael I. Ferguson	Enabling the On-line Intrinsic Evolution of Analog Controllers.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
17	Abhishek Somani, P. P. Chakrabarti 0001, Amit Patra	A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
17	Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Automatic Device Layout Generation for Analog Layout Retargeting.	VLSI Design	2005	DBLP DOI BibTeX RDF
17	Yang Xu 0017, Kan-Lin Hsiung, Xin Li 0001, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi	OPERA: optimization with ellipsoidal uncertainty for robust analog IC design.	DAC	2005	DBLP DOI BibTeX RDF	optimization, statistical
17	Fernando De Bernardinis, Pierluigi Nuzzo 0001, Alberto L. Sangiovanni-Vincentelli	Mixed signal design space exploration through analog platforms.	DAC	2005	DBLP DOI BibTeX RDF
17	Sule Ozev, Alex Orailoglu	Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF