Search results for "maze"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar	Steiner tree optimization for buffers, blockages, and bays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
11	Thomas G. Dietterich, Xin Wang 0010	Support Vectors for Reinforcement Learning.	PKDD	2001	DBLP DOI BibTeX RDF
11	Marco Balsi, Alessandro Maraschini, Giada Apicella, Sonia Luengo, Jordi Solsona, Xavier Vilasís-Cardona	Cellular Neural Networks for Mobile Robot Vision.	IWANN (2)	2001	DBLP DOI BibTeX RDF
11	K. K. Lee, D. F. Wong 0001	LRoute: a delay minimal router for hierarchical CPLDs.	FPGA	2001	DBLP DOI BibTeX RDF	complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation
11	Martin V. Butz	Biasing Exploration in an Anticipatory Learning Classifier System.	IWLCS	2001	DBLP DOI BibTeX RDF
11	Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar	Steiner tree optimization for buffers. Blockages and bays.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
11	Kai Jakobs	Standardization in Information Technology - Minitrack Introduction.	HICSS	2001	DBLP DOI BibTeX RDF
11	Thomas G. Dietterich, Xin Wang 0010	Support Vectors for Reinforcement Learning.	ECML	2001	DBLP DOI BibTeX RDF
11	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Hai Zhou 0001, Martin D. F. Wong, I-Min Liu, Adnan Aziz	Simultaneous routing and buffer insertion with restrictions onbuffer locations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Vijay Lakamraju, Russell Tessier	Tolerating operational faults in cluster-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
11	Sandeep N. Bhatt, Shimon Even, David S. Greenberg, Rafi Tayar	Traversing Directed Eulerian Mazes.	WG	2000	DBLP DOI BibTeX RDF
11	Bernard K. Gunther	The Circuit Object Organization Library.	ACAC	2000	DBLP DOI BibTeX RDF
11	Yao-Wen Chang, Yu-Tsang Chang	An architecture-driven metric for simultaneous placement and global routing for FPGAs.	DAC	2000	DBLP DOI BibTeX RDF
11	Tsai-Yen Li, Hung-Kai Ting	An Intelligent User Interface with Motion Planning for 3D Navigation.	VR	2000	DBLP DOI BibTeX RDF	Randomized Roadmap, 3D Navigation Control, VRML, Path Planning, Intelligent User Interface
11	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
11	Andre Plante, Shoji Tanaka, Yuichi Iwadate	Virtual Shinto Shrine.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF	image-based VR, artistic treatment, panoramic image
11	Diana Slattery, William Brubaker, Daniel O'Neil	Mazes and Morphs: Modeling Meaning in Glide, a Non-Linear, Dynamic Visual Language.	VL	1999	DBLP DOI BibTeX RDF	visual language, art, narrative, metaphor, cognitive linguistics
11	Andy Tomlinson, Larry Bull	A Corporate Classifier System.	PPSN	1998	DBLP DOI BibTeX RDF
11	Asmus Hetzel	A Sequential Detailed Router for Huge Grid Graphs.	DATE	1998	DBLP DOI BibTeX RDF	Rip-up And Reroute, Shortest Paths, Detailed Routing
11	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	ISPD	1998	DBLP DOI BibTeX RDF
11	Uta Ziegler	Extending an iterator model for binary trees to backtracking problems.	SIGCSE	1998	DBLP DOI BibTeX RDF
11	David A. Mix Barrington, Chi-Jen Lu, Peter Bro Miltersen, Sven Skyum	Searching Constant Width Mazes Captures the AC0 Hierarchy.	STACS	1998	DBLP DOI BibTeX RDF
11	Jason Cong, Patrick H. Madden	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
11	Ramiro Liscano, Reda E. Fayek, Allan Manz, Elizabeth R. Stuck, Jean-Yves Tigli	Using a Blackboard to Integrate Multiple Activities and Achieve Strategic Reasoning for Mobile-Robot Navigation.	IEEE Expert	1995	DBLP DOI BibTeX RDF
11	Ioan I. Macarie	On the Structure of Log-Space Probabilistic Complexity Classes (Extended Abstract).	STACS	1995	DBLP DOI BibTeX RDF
11	Raja Venkateswaran, Pinaki Mazumder	Coprocessor design for multilayer surface-mounted PCB routing.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
11	Helmar Burkhart, Rudolf Eigenmann, Heinz Kindlimann, Michael Moser, Heinz Scholian	The M3 Multiprocessor Laboratory.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	M/sup 3/ multiprocessor laboratory, integrated programming environment, softwaredevelopment cycle, parallel program, parallel programming, debugging, programming, programming environments, performance measurement, configuration
11	Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli	Area routing for analog layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Tahsin M. Kurç, Cevdet Aykanat, Fikret Erçal	Parallelization of Lee's Routing Algorithm on a Hypercube Multicomputer.	EDMCC	1991	DBLP DOI BibTeX RDF
11	Jonathan Rose	Parallel global routing for standard cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
11	Dwight D. Hill, Don Shugard	Global Routing Considerations in a Cell Synthesis System.	DAC	1990	DBLP DOI BibTeX RDF
11	Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma	Techniques for multilayer channel routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
11	Ivan B. Liss, Thomas C. McMillan	An amazing exercise in recursion for CS1 and CS2.	SIGCSE	1988	DBLP DOI BibTeX RDF
11	Jonathan Rose	LocusRoute: A Parallel Global Router for Standard Cells.	DAC	1988	DBLP BibTeX RDF
11	Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli	Chameleon: a new multi-layer channel router.	DAC	1986	DBLP DOI BibTeX RDF
11	Wing K. Luk, Donald T. Tang, C. K. Wong	Hierarchial global wiring for custom chip design.	DAC	1986	DBLP DOI BibTeX RDF
11	James F. Teixeira, Roy P. Sallen	The Sylvania data tablet: a new approach to graphic data input.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
11	John J. Dent	Diagnostic engineering requirements.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF