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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 455 occurrences of 313 keywords
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Results
Found 754 publication records. Showing 754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme |
Application of Reconfigurable CORDIC Architectures. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon |
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Achim Freimann |
Framework for High-Level Power Estimation of Signal Processing Architectures. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Yoochang Jung, Yukio Chiba, Donglok Kim, Yongmin Kim 0001 |
simCore: An Event-Driven Simulation Framework for Performance Evaluation of Computer Systems. |
MASCOTS |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Joerg Abke, Erich Barke |
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Basant Rajan, R. K. Shyamasundar |
Multiclock Esterel: A Reactive Framework for Asynchronous Design. |
IPDPS |
2000 |
DBLP DOI BibTeX RDF |
VHDL, Reactive Systems, Asynchronous System, Synchrony, Esterel |
10 | Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba |
Recover-X: An Adaptive Router with Limited Escape Channels. |
ICPADS |
2000 |
DBLP DOI BibTeX RDF |
wormhole routers, adaptive routing, hardware description language, hardware cost, deadlock recovery |
10 | Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee |
Formal Verification of an Industrial System-on-a-Chip. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra |
Hierarchical Simulation of a Multiprocessor Architecture. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai |
BRAINS: A BIST Compiler for Embedded Memories. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Christoph Meinel, Christian Stangier |
Speeding Up Image Computation by Using RTL Information. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Dennis Abts, Mike Roberts, David J. Lilja |
A Balanced Approach to High-Level Verification: Performance Trade-Offs in Verifying Large-Scale Multiprocessors. |
ICPP |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Arun K. Majumdar, Nirav Patel |
Design of an ASIC for Straight Line Detection in an Image. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Hough Transform, CORDIC, ASIC Design |
10 | Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta 0001 |
Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Yang Xia, Pranav Ashar |
Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol |
10 | Steven Trimberger, Raymond Pang, Amit Singh |
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. |
CHES |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Ramesh Radhakrishnan, Deependra Talla, Lizy Kurian John |
Allowing for ILP in an embedded Java processor. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Marcelino B. Santos, João Paulo Teixeira 0001 |
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta |
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Masayuki Takahashi, Kimihiro Ogawa, Kenneth S. Kundert |
VCO Jitter Simulation and Its Comparison With Measurement. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Susan A. Mengel, Joseph V. Ulans |
A Case Study of the Analysis of Novice Student Programs. |
CSEE&T |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Donald W. Bouldin, Senthil Natarajan, Benjamin A. Levine, Chandra Tan, Danny F. Newport |
Training IP Creators and Integrators. |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Ryuichi Takahashi, Noriyoshi Yoshida |
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Susan A. Mengel, Vinay Yerramilli |
A case study of the static analysis of the quality of novice student programs. |
SIGCSE |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew I. Frank, Rajeev Barua, Saman P. Amarasinghe |
Parallelizing Applications into Silicon. |
FCCM |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Damian Dalton |
Analysis of an Associative Array Parallel Logic Simulator. |
ICPP Workshops |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Srivatsan Srinivasan, Lizy Kurian John |
On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer |
10 | Eduard Cerny, Fen Jin |
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Interface verification, interface controllers, relational interval arithmetic, constraint logic programming, timing verification, timing diagrams |
10 | Huimin Xia, Khaldoun Bataineh, Marwan Hassoun, Joe Kryzak |
A mixed-signal behavioral level implementation of 1000BASE-X physical layer for gigabit Ethernet. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | C.-C. Wang, C. J. Huang, P.-M. Lee |
A comparison of two alternative architectures of digital ratioed compressor design for inner product processing. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | C.-C. Wang, C. J. Huang, G.-C. Lin |
A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | E. K. Ogoubi, Eduard Cerny |
Synthesis of checker EFSMs from timing diagram specifications. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Swarup Bhunia, Soumya K. Ghosh 0001, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee 0001 |
Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Kwang-Il Park, Kyu Ho Park |
Event suppression by optimizing VHDL programs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Wilfred Corrigan |
ASIC Challenges: Emerging from a Primordial Soup. |
IEEE Des. Test Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Ratan Nalumasu, Rajnish Ghughal, Abdelillah Mokkedem, Ganesh Gopalakrishnan |
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors. |
CAV |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton |
Structural Symmetry and Model Checking. |
CAV |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Juan Carlos Diaz, Pierre Plaza, Jesus Crespo |
ATM Traffic Shaper: ATS. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
ATM, Traffic Shaping, FPGA Prototyping |
10 | A. C. Verschueren |
Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description Languages. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Jianping Lu, Sofiène Tahar |
Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Ásgeir Th. Eiríksson |
The Formal Design of 1M-gate ASICs. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Defect-oriented test quality assessment using fault sampling and simulation. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Roberto Passerone, James A. Rowson, Alberto L. Sangiovanni-Vincentelli |
Automatic Synthesis of Interfaces Between Incompatible Protocols. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
10 | Franco Fummi, U. Rovati, Donatella Sciuto |
Functional design for testability of control-dominated architectures. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
interacting FSMs, functional testing |
10 | Kwang-Il Park, Jun Sung Kim, Heung Bum Kim, Jong Hyuk Choi, Kyu Ho Park |
The Acceleration of VHDL Simulation by Classifying Events. |
Annual Simulation Symposium |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Jonathan Babb, Matthew I. Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael B. Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal |
The RAW benchmark suite: computation structures for general purpose computing. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Vincent John Mooney III, Giovanni De Micheli |
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
worst-case execution time, rtos, hardware-software codesign, real-time analysis, run-time scheduler |
10 | Franco Fummi, Mariagiovanna Sami, F. Tartarini |
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. |
Great Lakes Symposium on VLSI |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Raghuram S. Tupuri, Jacob A. Abraham |
A Novel Hierarchical Test Generation Method for Processors. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Ashley Rasquinha, N. Ranganathan |
C3L: A Chip for Connected Component Labeling. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Jian Li 0061, Rajesh K. Gupta 0001 |
Limited Exception Modeling and Its Use in Presynthesis Optimizations. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Ghassan Al Hayek, Chantal Robach |
On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification |
10 | Jennifer Rexford, John Hall, Kang G. Shin |
A Router Architecture for Real-Time Point-to-Point Networks. |
ISCA |
1996 |
DBLP DOI BibTeX RDF |
|
10 | Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill |
Architecture Validation for Processors. |
ISCA |
1995 |
DBLP DOI BibTeX RDF |
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