Search results for "ASP-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran	Routing perturbation for enhanced security in split manufacturing.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura	An image sensor/processor 3D stacked module featuring ThruChip interfaces.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Mingze Gao, Qian Wang 0022, Akshaya S. Kankanhalli-Nagendra, Gang Qu 0001	A novel data format for approximate arithmetic computing.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Ye Zhang 0011, Wai-Shing Luk, Fan Yang 0001, Changhao Yan, Hai Zhou 0001, Dian Zhou, Xuan Zeng 0001	Network flow based cut redistribution and insertion for advanced 1D layout design.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou	Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	M. Hassan Najafi, David J. Lilja	High-speed stochastic circuits using synchronous analog pulses.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang 0001, Tseng-Yi Chen, Hsin-Wen Wei, Wei-Kuan Shih	KVFTL: Optimization of storage space utilization for key-value-specific flash storage devices.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler	Exact routing for micro-electrode-dot-array digital microfluidic biochips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato	Efficient circuit failure probability calculation along product lifetime considering device aging.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kent Gauen, Rohit Rangan, Anup Mohan, Yung-Hsiang Lu, Wei Liu 0015, Alexander C. Berg	Low-power image recognition challenge.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	A novel basis for logic rewriting.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta	A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Dimitrios Tychalas, Nektarios Georgios Tsoutsos, Michail Maniatakos	SGXCrypter: IP protection for portable executables using Intel's SGX technology.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Chuhan Min, Jie Guo 0002, Hai Li 0001, Yiran Chen 0001	Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Meng Liu 0001, Matthias Becker 0004, Moris Behnam, Thomas Nolte	Using segmentation to improve schedulability of RRA-based NoCs with mixed traffic.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Caiwen Ding, Ji Li 0006, Weiwei Zheng, Naehyuck Chang, Xue Lin, Yanzhi Wang	Algorithm accelerations for luminescent solar concentrator-enhanced reconfigurable onboard photovoltaic system.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Cunxi Yu, Maciej J. Ciesielski	Efficient parallel verification of Galois field multipliers.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang	Delay-driven layer assignment for advanced technology nodes.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	K. T. Tim Cheng	ASP-DAC 2017 keynote speech I-1: Heterogeneous integration of X-tronics: Design automation and education.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Ching-Wei Hsieh, Zipeng Li, Tsung-Yi Ho	Piracy prevention of digital microfluidic biochips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Lin Cheng 0001, Wing-Hung Ki, Tak-Sang Yim	A 13.56 MHz on/off delay-compensated fully-integrated active rectifier for biomedical wireless power transfer systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Zuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh 0002, Wei Zhang 0012, Yingnan Cui	Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Archit Gupta, Tianshi Wang, Ahmet Mahmutoglu Gokcen, Jaijeet Roychowdhury	STEAM: Spline-based tables for efficient and accurate device modelling.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Li-Pin Chang, Chia-Hsiang Cheng, Kai-Hsiang Lin	A flash scheduling strategy for current capping in multi-power-mode SSDs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Marta Ortín-Obón, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi	A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa	W-band ultra-high data-rate 65nm CMOS wireless transceiver.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Ho Hyun Shin, Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim 0001, Eui-Young Chung	Timing window wiper: A new scheme for reducing refresh power of DRAM.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta	Non-binary cyclic ADC with correlated level shifting technique.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yibin Tang, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Jan Malburg, Tino Flenker, Görschwin Fey	Property mining using dynamic dependency graphs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yi Wang 0003, Mingxu Zhang, Jing Yang 0018	Temperature-aware data allocation strategy for 3D charge-trap flash memory.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Lei Yang 0018, Weichen Liu, Nan Guan, Mengquan Li, Peng Chen 0027, Edwin Hsing-Mean Sha	Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Tim Schmidt, Guantao Liu, Rainer Dömer	Hybrid analysis of SystemC models for fast and accurate parallel simulation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kun-Lin Lin, Shao-Yun Fang	Guiding template-aware routing considering redundant via insertion for directed self-assembly.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Atsuki Kobayashi, Kei Ikeda, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato, Kiichi Niitsu	Design of an energy-autonomous bio-sensing system using a biofuel cell and 0.19V 53μW integrated supply-sensing sensor with a supply-insensitive temperature sensor and inductive-coupling transmitter.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Katsumi Okuda, Minoru Yoshida, Haruhiko Takeyama, Minoru Nakamura	Automated generation of dynamic binary translators for instruction set simulation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Ji Li 0006, Ao Ren, Zhe Li 0001, Caiwen Ding, Bo Yuan 0001, Qinru Qiu, Yanzhi Wang	Towards acceleration of deep convolutional neural networks using stochastic computing.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yijin Guan, Zhihang Yuan, Guangyu Sun 0003, Jason Cong	FPGA-based accelerator for long short-term memory recurrent neural networks.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu	Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Heinz Riener, Rüdiger Ehlers, Görschwin Fey	CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Aosen Wang, Chi Zhou 0004, Zhanpeng Jin, Wenyao Xu	Towards scalable and efficient GPU-enabled slicing acceleration in continuous 3D printing.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yandan Wang, Wei Wen, Linghao Song, Hai Helen Li	Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yoichi Tomioka, Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima	Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Fan Lin, Kwang-Ting Cheng	An artificial neural network approach for screening test escapes.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Varsha Agarwal, Ananya Singla, Mahammad Samiuddin, Sudip Roy 0001, Tsung-Yi Ho, Indranil Sengupta 0001, Bhargab B. Bhattacharya	Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Fan Lan, Rui Wu 0008, Chong Zhang, Yun Pan, Kwang-Ting (Tim) Cheng	DLPS: Dynamic laser power scaling for optical Network-on-Chip.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yang You, Jie Gu	Exploiting accelerated aging effect for on-line configurability and hardware tracking.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada	CMOS-on-quartz pulse generator for low power applications.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Cheng Wang, Ying Wang 0001, Yinhe Han 0001, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li 0001	CNN-based object detection solutions for embedded heterogeneous multicore SoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hyeon Uk Sim, Dong Nguyen 0001, Jongeun Lee, Kiyoung Choi	Scalable stochastic-computing accelerator for convolutional neural networks.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1		22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017	ASP-DAC	2017	DBLP BibTeX RDF
1	Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, Yongpan Liu, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan	Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Guan-Ruei Lu, Guan-Ming Huang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen	On reliability hardening in cyber-physical digital-microfluidic biochips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yi Lin, Po-Chun Huang, Duo Liu, Liang Liang 0002	Scalable frequent-pattern mining on nonvolatile memories.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu	Majority logic circuits optimisation by node merging.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Lin Cheng 0001, Wing-Hung Ki, Chi-Ying Tsui	A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Deming Chen	ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Xiaokun Yang, Wujie Wen	Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Zhongming Chen, Kim Batselier, Haotian Liu, Ngai Wong	An efficient homotopy-based Poincaré-Lindstedt method for the periodic steady-state analysis of nonlinear autonomous oscillators.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori	A 19-μA metabolic equivalents monitoring SoC using adaptive sampling.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw	Design considerations and clinical applications of closed-loop neural disorder control SoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hussam Amrouch, Jörg Henkel	Containing guardbands.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	John Adler, Ryan Berryhill, Andreas G. Veneris	An extensible perceptron framework for revision RTL debug automation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Xuechao Wei, Yun Liang 0001, Tao Wang 0004, Songwu Lu, Jason Cong	Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi 0001, Shih-Chieh Chang	Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kuo-Kai Hsieh, Sebastian Siatkowski, Li-C. Wang, Wen Chen 0016, Jayanta Bhadra	Feature extraction from design documents to enable rule learning for improving assertion coverage.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Md Tanvir Arafin, Mingze Gao, Gang Qu 0001	VOLtA: Voltage over-scaling based lightweight authentication for IoT applications.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Jun Ohta	Smart electrode - toward a retinal stimulator with the large number of electrodes.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Tianqi Tang 0001, Lixue Xia, Boxun Li, Yu Wang 0002, Huazhong Yang	Binary convolutional neural network on RRAM.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li 0002, José Pineda de Gyvez	Floorplan and placement methodology for improved energy reduction in stacked power-domain design.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Biruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco	AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yi Wu, Chuyu Shen, Yi Jia, Weikang Qian	Approximate logic synthesis for FPGA by wire removal and local function change.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Chenchen Liu, Qing Yang 0011, Chi Zhang, Hao Jiang 0014, Qing Wu 0002, Hai Helen Li	A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Ao Ren, Sijia Liu 0001, Ruizhe Cai, Wujie Wen, Pramod K. Varshney, Yanzhi Wang	Algorithm-hardware co-optimization of the memristor-based framework for solving SOCP and homogeneous QCQP problems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei	Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler	Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Nicole Fern, Ismail San, Kwang-Ting (Tim) Cheng	Detecting hardware Trojans in unspecified functionality through solving satisfiability problems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata	An FPGA-compatible PLL-based sensor against fault injection attack.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	Multi-level logic benchmarks: An exactness study.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Meng Liu 0001, Matthias Becker 0004, Moris Behnam, Thomas Nolte	A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui	BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Kohei Gamo, Kazuo Nakazato, Kiichi Niitsu	A current-integration-based CMOS amperometric sensor with 1.2 μm × 2.05 μm electroless-plated microelectrode array for high-sensitivity bacteria counting.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Zihao Liu, Wujie Wen, Lei Jiang 0001, Yier Jin, Gang Quan	A statistical STT-RAM retention model for fast memory subsystem designs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang	Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Qin Wang 0005, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li 0005, Ulf Schlichtmann, Yici Cai	Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor	Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao	Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Arvind Easwaran, Anupam Chattopadhyay, Shivam Bhasin	A systematic security analysis of real-time cyber-physical systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Tuotian Liao, Lihong Zhang	Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hui Zhang, Bo Wang	A time domain behavioral model for oscillators considering flicker noise.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Francesco Regazzoni 0001, Ilia Polian	Securing the hardware of cyber-physical systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Hiroto Yasuura	ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Liu Liu 0017, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie 0001	Building energy-efficient multi-level cell STT-RAM caches with data compression.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Dharanidhar Dang, Sai Vineel Reddy Chittamuru, Rabi N. Mahapatra, Sudeep Pasricha	Islands of heaters: A novel thermal management framework for photonic NoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Yangguo Liu, Junlin Lu, Dong Tong 0001, Xu Cheng 0001	Locality-aware bank partitioning for shared DRAM MPSoCs.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Sujit Rokka Chhetri, Jiang Wan, Mohammad Abdullah Al Faruque	Cross-domain security of cyber-physical systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
1	Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia	MUTARCH: Architectural diversity for FPGA device and IP security.	ASP-DAC	2017	DBLP DOI BibTeX RDF

Publications at "ASP-DAC"( http://dblp.L3S.de/Venues/ASP-DAC )