Search results for "Codesign"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Clément Foucher, Fabrice Muller, Alain Giulieri	Online codesign on reconfigurable platform for parallel computing.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
16	Angeliki Kritikakou, Francky Catthoor, George Athanasiou, Vasilios I. Kelefouras, Costas E. Goutis	Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
16	Nejdat Demirel, Yenny Pinto, Christophe Calvez, Diane Titz, Cyril Luxey, Christian Person, Daniel Gloria, Didier Belot, Denis Pache, Eric Kerherve	Codesign of a PA-Antenna Block in Silicon Technology for 80-GHz Radar Application.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
16	David J. Kuck	Keynote talk: A comprehensive approach to HW/SW codesign.	PACT	2013	DBLP DOI BibTeX RDF
16		11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMCODE 2013, Portland, OR, USA, October 18-20, 2013	MEMOCODE	2013	DBLP BibTeX RDF
16	David Sheffield, Michael J. Anderson, Yunsup Lee, Kurt Keutzer	Hardware/software codesign for mobile speech recognition.	INTERSPEECH	2013	DBLP DOI BibTeX RDF
16	Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan	Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform.	ISED	2013	DBLP DOI BibTeX RDF
16	Sanad Al-Areqi, Daniel Görges, Sven Reimann, Steven Liu	Event-based control and scheduling codesign of networked embedded control systems.	ACC	2013	DBLP DOI BibTeX RDF
16	Sven Reimann, Sanad Al-Areqi, Steven Liu	Output-based control and scheduling codesign for control systems sharing a limited resource.	CDC	2013	DBLP DOI BibTeX RDF
16	Martin C. Herbordt	Architecture/algorithm codesign of molecular dynamics processors.	ACSSC	2013	DBLP DOI BibTeX RDF
16	Hung-Ming Chen	On the way to practical tools for beyond die codesign and integration.	ISPD	2013	DBLP DOI BibTeX RDF
16	Ardavan Pedram	Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics.	IPDPS Workshops	2013	DBLP DOI BibTeX RDF
16		Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, Montreal, QC, Canada, September 29 - October 4, 2013	CODES+ISSS	2013	DBLP BibTeX RDF
16	Ranko Sredojevic, Andrew Wright, Vladimir Stojanovic	Hardware-Software Codesign for Embedded Numerical Acceleration.	FCCM	2013	DBLP DOI BibTeX RDF
16	Takuya Azumi, Yasaman Samei Syahkal, Yuko Hara-Azumi, Hiroshi Oyama 0002, Rainer Dömer	TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component.	IESS	2013	DBLP DOI BibTeX RDF
16	Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim	SESH Framework: A Space Exploration Framework for GPU Application and Hardware Codesign.	PMBS@SC	2013	DBLP DOI BibTeX RDF
16	Yuan-Kai Ho, Yao-Wen Chang	Multiple chip planning for chip-interposer codesign.	DAC	2013	DBLP DOI BibTeX RDF
16	Ahmet Turan Erozan, Subutay Giray Baskir, Siddika Berna Örs	Hardware/Software codesign for watermarking in DCT domain.	SIU	2013	DBLP DOI BibTeX RDF
16	Alessandra Talamo, Stefano Ventura, Sabina Giorgi, Miguel Ceriani, Paolo Bottoni, Barbara Mellini	"Do the gestures you think of": creating affordances in codesign.	CHItaly	2013	DBLP DOI BibTeX RDF
16	Ranko Sredojevic	Template-based hardware-software codesign for high-performance embedded numerical accelerators.		2013	RDF
16	Myron King	A methodology for hardware-software codesign.		2013	RDF
16	Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione	Fast prototyping from assertions: A pragmatic approach.	MEMOCODE	2013	DBLP BibTeX RDF
16	Florin Balasa, Ilie I. Luican, Noha Abuaesh, Cristian V. Gingu	Compiler-directed memory hierarchy design for low-energy embedded systems.	MEMOCODE	2013	DBLP BibTeX RDF
16	Lee Pike	Keynote talk I: Building a high-assurance unpiloted air vehicle.	MEMOCODE	2013	DBLP BibTeX RDF
16	Jungwook Choi, Rob A. Rutenbar	FPGA acceleration of Markov Random Field TRW-S inference for stereo matching.	MEMOCODE	2013	DBLP BibTeX RDF
16	Carlos Villarraga, Bernard Schmidt, Jörg Bormann, Christian Bartsch 0001, Dominik Stoffel, Wolfgang Kunz	An equivalence checker for hardware-dependent embedded system software.	MEMOCODE	2013	DBLP BibTeX RDF
16	Vidura Wijaysekara, Sudarshan K. Srinivasan	Equivalence checking for synchronous elastic circuits.	MEMOCODE	2013	DBLP BibTeX RDF
16	Robert de Groote, Philip K. F. Hölzenspies, Jan Kuper, Hajo Broersma	Back to basics: Homogeneous representations of multi-rate synchronous dataflow graphs.	MEMOCODE	2013	DBLP BibTeX RDF
16	Yatin Hoskote	Keynote talk II: Designing tomorrow's chips.	MEMOCODE	2013	DBLP BibTeX RDF
16	Harry Foster	Keynote talk III: Industry pulse: Trends in function verification.	MEMOCODE	2013	DBLP BibTeX RDF
16	Manuel Gesell, Klaus Schneider 0001	Translating synchronous guarded actions to interleaved guarded actions.	MEMOCODE	2013	DBLP BibTeX RDF
16	Rajeev Alur	Tutorial I: Syntax-guided synthesis.	MEMOCODE	2013	DBLP BibTeX RDF
16	Sayak Ray, Robert K. Brayton	Ranking structure in communication fabrics.	MEMOCODE	2013	DBLP BibTeX RDF
16	Saddek Bensalem, Axel Legay, Ayoub Nouri, Doron A. Peled	Synthesizing distributed scheduling implementation for probabilistic component-based systems.	MEMOCODE	2013	DBLP BibTeX RDF
16	Frédéric Mallet, Jean-Vivien Millo, Robert de Simone	Safe CCSL specifications and marked graphs.	MEMOCODE	2013	DBLP BibTeX RDF
16	Muralidaran Vijayaraghavan, Nirav Dave, Arvind	Modular compilation of guarded atomic actions.	MEMOCODE	2013	DBLP BibTeX RDF
16	Matthew Anderson, Sandeep K. Shukla	APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study.	MEMOCODE	2013	DBLP BibTeX RDF
16	Cynthia Sturton, Rohit Sinha 0001, Thurston H. Y. Dang, Sakshi Jain, Michael McCoyd, Wei Yang Tan, Petros Maniatis, Sanjit A. Seshia, David A. Wagner 0001	Symbolic software model validation.	MEMOCODE	2013	DBLP BibTeX RDF
16	Firew Siyoum, Marc Geilen, Johan Eker, Carl von Platen, Henk Corporaal	Automated extraction of scenario sequences from disciplined dataflow networks.	MEMOCODE	2013	DBLP BibTeX RDF
16	Hassan Eslami, Theodoros Kasampalis, Maria Kotsifakou	A GPU implementation of tiled belief propagation on Markov Random Fields.	MEMOCODE	2013	DBLP BibTeX RDF
16	Eriko Nurvitadhi	MEMOCODE 2013 hardware/software co-design contest: Stereo matching.	MEMOCODE	2013	DBLP BibTeX RDF
16	Sebastiaan J. C. Joosten, Julien Schmaltz	Generation of inductive invariants from register transfer level designs of communication fabrics.	MEMOCODE	2013	DBLP BibTeX RDF
16	Armin Ahmadzadeh, Hatef Madani, Kianoush Jafari, Farzad Salimi Jazi, Shervin Daneshpajouh, Saeid Gorgin 0001	Fast and adaptive BP-based multi-core implementation for stereo matching.	MEMOCODE	2013	DBLP BibTeX RDF
16	Hichem Debbi, Mustapha Bourahla	Causal analysis of probabilistic counterexamples.	MEMOCODE	2013	DBLP BibTeX RDF
16	Thomas Kuhn 0001, Thomas Forster, Tobias Braun, Reinhard Gotzhein	FERAL - Framework for simulator coupling on requirements and architecture level.	MEMOCODE	2013	DBLP BibTeX RDF
16	Wei Wang, Miodrag Bolic, Jonathan Parri	pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Shuo Li 0002, Nasim Farahini, Ahmed Hemani, Kathrin Rosvall, Ingo Sander	System level synthesis of hardware for DSP applications using pre-characterized function implementations.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer	Automated, retargetable back-annotation for host compiled performance and power modeling.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Abbas Rahimi, Andrea Marongiu, Rajesh K. Gupta 0001, Luca Benini	A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Ke Bai 0002, Jing Lu 0003, Aviral Shrivastava, Bryce Holton	CMSM: An efficient and effective Code Management for Software Managed Multicores.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Kevin M. Irick	Embedded neuromorphic vision systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Nicola Bombieri, Franco Fummi, Sara Vinco	On the automatic generation of GPU-oriented software applications from RTL IPs.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Wanli Chang 0001, Martin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty	Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Lide Zhang, David R. Bild, Robert P. Dick, Zhuoqing Morley Mao, Peter A. Dinda	Panappticon: Event-based tracing to measure mobile application and platform performance.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Laurence Pierre, Zeineb Bel Hadj Amor	Automatic refinement of requirements for verification throughout the SoC design flow.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Olivier Temam	Hardware neural network accelerators.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Yue Gao, Yanzhi Wang, Sandeep K. Gupta 0001, Massoud Pedram	An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Jan R. Seyler	Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Aaron Severance, Guy G. F. Lemieux	Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Mengying Zhao, Hao Zhang, Xiang Chen 0010, Yiran Chen 0001, Chun Jason Xue	Online OLED dynamic voltage scaling for video streaming applications on mobile devices.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Di Zhu 0002, Siyu Yue, Yanzhi Wang, Younghyun Kim 0001, Naehyuck Chang, Massoud Pedram	Designing a residential hybrid electrical energy storage system based on the energy buffering strategy.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Francesco Conti 0001, Andrea Marongiu, Luca Benini	Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Michele Bertasi, Giuseppe Di Guglielmo, Graziano Pravadelli	Automatic generation of compact formal properties for effective error detection.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Chien-Chung Ho, Po-Chun Huang, Yuan-Hao Chang 0001, Tei-Wei Kuo	A DRAM-flash index for native flash file systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Sven Goossens, Jasper Kuijsten, Benny Akesson, Kees Goossens	A reconfigurable real-time SDRAM controller for mixed time-criticality systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Radu Marculescu, Preeti Ranjan Panda	Message from the program co-chairs.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Da-Cheng Juan, Siddharth Garg, Jinpyo Park, Diana Marculescu	Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich	Run-time adaption for highly-complex multi-core systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Kristofor D. Carlson, Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar	Design space exploration and parameter tuning for neuromorphic applications.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Joseph Tarango, Eamonn J. Keogh, Philip Brisk	Instruction set extensions for Dynamic Time Warping.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Majid Namaki-Shoushtari, Abbas Rahimi, Nikil D. Dutt, Puneet Gupta 0001, Rajesh K. Gupta 0001	ARGO: Aging-aware GPGPU register file allocation.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Sebastian Graf 0002, Michael Glaß, Dominic Wintermann, Jürgen Teich, Christoph Lauer	IVaM: Implicit variant modeling and management for automotive embedded systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Lucas Francisco Wanner, Salma Elmalaki 0001, Liangzhen Lai, Puneet Gupta 0001, Mani B. Srivastava	VarEMU: An emulation testbed for variability-aware software.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Moritz Neukirchner, Kai Lampka, Sophie Quinton, Rolf Ernst	Multi-mode monitoring for mixed-criticality real-time systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Wei Zuo, Peng Li 0031, Deming Chen, Louis-Noël Pouchet, Shunan Zhong, Jason Cong	Improving polyhedral code generation for high-level synthesis.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Joël Porquet, Simha Sethumadhavan	WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Renhai Chen, Yi Wang 0003, Zili Shao	DHeating: Dispersed heating repair for self-healing NAND flash memory.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Mahboobeh Ghorbani, Paul Bogdan	A cyber-physical system approach to artificial pancreas design.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Jean-Philippe Diguet, Marius Strum, Nicolas Le Griguer, Lydie Caetano, Martha Johanna Sepúlveda	Scalable NoC-based architecture of neural coding for new efficient associative memories.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Beiye Liu, Miao Hu, Hai Li 0001, Yiran Chen 0001, Chun Xue	Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Mingsong Chen, Lei Zhou 0007, Geguang Pu, Jifeng He 0001	Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Fazal Hameed, Lars Bauer, Jörg Henkel	Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Koichi Tokuno	Codesign-Oriented and User-Perceived Service Availability Measurement for Hardware/Software System.	Asia Pac. J. Oper. Res.	2012	DBLP DOI BibTeX RDF
16	Ardavan Pedram, Robert A. van de Geijn, Andreas Gerstlauer	Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
16	Ahmed Abousamra, Alex K. Jones, Rami G. Melhem	Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2012	DBLP DOI BibTeX RDF
16	Soonhoi Ha	Prolog to the Section on Hardware/Software Codesign.	Proc. IEEE	2012	DBLP DOI BibTeX RDF
16	Jürgen Teich	Hardware/Software Codesign: The Past, the Present, and Predicting the Future.	Proc. IEEE	2012	DBLP DOI BibTeX RDF
16	Ramzi Darraji, Fadhel M. Ghannouchi	RF/DSP Codesign Methodology of Enhanced Doherty Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
16	David J. Kuck	Computational Capacity-Based Codesign of Computer Systems.	High-Performance Scientific Computing	2012	DBLP DOI BibTeX RDF
16		Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMCODE 2012, Arlington, VA, USA, July 16-17, 2012	MEMOCODE	2012	DBLP BibTeX RDF
16	Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero 0002, Raúl Valencia	COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration.	DSD	2012	DBLP DOI BibTeX RDF
16	Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer	FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels.	DSD	2012	DBLP DOI BibTeX RDF
16	Ignacio Peñarrocha, Daniel Dolz, Julio-Ariel Romero-Pérez, Roberto Sanchis 0001	Codesign strategy of inferential controllers for wireless sensor networks.	ICUMT	2012	DBLP DOI BibTeX RDF
16	Sven Reimann, Wei Wu, Steven Liu	A novel control-schedule codesign method for embedded control systems.	ACC	2012	DBLP DOI BibTeX RDF
16	Andrew K. Bolstad, Benjamin A. Miller, Karen Gettings, Mike Ericson, Helen Kim, Merlin Green, Dan Santiago	Sparse polynomial equalization of an RF receiver via algorithm, analog, and digital codesign.	ACSCC	2012	DBLP DOI BibTeX RDF
16	Ahmed Jerraya, Luca P. Carloni, Naehyuck Chang, Franco Fummi (eds.)	Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012		2012	DBLP DOI BibTeX RDF
16	Markus Weinhardt	Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform.	ARC	2012	DBLP DOI BibTeX RDF
16	Richard F. Barrett, Xiaobo Sharon Hu, Sudip S. Dosanjh, Steven G. Parker, Michael A. Heroux, John Shalf	Toward codesign in high performance computing systems.	ICCAD	2012	DBLP DOI BibTeX RDF
16	Shin-Kai Chen, Sheng-Yun Wu, Yu-Kai Yen, Chih-Wei Liu	Early Stage Codesign of Multi-PE SIMD Engine: A Case Study on Object Detection.	ICPP Workshops	2012	DBLP DOI BibTeX RDF
16	Chunsheng Li, Xi Li 0003, Chao Wang 0003, Xuehai Zhou, Fangling Zeng	A Dependency Aware Task Partitioning and Scheduling Algorithm for Hardware-Software Codesign on MPSoCs.	ICA3PP (1)	2012	DBLP DOI BibTeX RDF