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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 210 occurrences of 148 keywords
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Results
Found 3186 publication records. Showing 3186 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Muhammed Al Kadi, Max Ferger, Volker Stegemann, Michael Hübner 0001 |
Multi-FPGA reconfigurable system for accelerating MATLAB simulations. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Kenji Kanazawa, Tsutomu Maruyama |
FPGA acceleration of SAT/Max-SAT solving using variable-way cache. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lei Xu 0012, Han-Yee Kim, Xi Wang 0011, Weidong Shi, Taeweon Suh |
Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Stefan Wonneberger, Max Kohler, Wojciech Derendarz, Thorsten Graf 0001, Rolf Ernst |
Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Siqi Wang, Pham Nam Khanh, Amit Kumar Singh 0002, Akash Kumar 0001 |
Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001 |
Fast and accurate SEU-tolerance characterization method for Zynq SoCs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Tim Güneysu, Francesco Regazzoni 0001, Pascal Sasdrich, Marcin Wójcik |
THOR - The hardware onion router. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Gary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk |
An efficient sparse conjugate gradient solver using a Beneš permutation network. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Eugene Cartwright, Alborz Sadeghian, Sen Ma, David Andrews 0001 |
Achieving portability and efficiency over chip heterogeneous multiprocessor systems. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Nima Safari, Volker Mauer, Shahin Gheitanchi |
Methods for implementation of feedback loops in high speed FPGA applications. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Soh Jun Jie, Nachiket Kapre |
Comparing soft and hard vector processing in FPGA-based embedded systems. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin |
A semi-supervised modeling approach for performance characterization of FPGA architectures. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen |
TransPar: Transformation based dynamic Parallelism for low power CGRAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Pohl, Michael Schaeferling, Gundolf Kiefer |
An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk |
Patra: Parallel tree-reweighted message passing architecture. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Henry Block, Tsutomu Maruyama |
An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi 0001, Mehdi Baradaran Tahoori |
Towards dark silicon era in FPGAs using complementary hard logic design. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar |
Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jasmina Vasiljevic, Paul Chow |
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Dirk Koch, Christian Beckhoff |
Hierarchical reconfiguration of FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Muhuan Huang, Kevin Lim, Jason Cong |
A scalable, high-performance customized priority queue. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Aiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa |
A soft-core processor for finite field arithmetic with a variable word size accelerator. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Joshua S. Monson, Brad L. Hutchings |
New approaches for in-system debug of behaviorally-synthesized FPGA circuits. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | |
24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014 |
FPL |
2014 |
DBLP BibTeX RDF |
|
1 | Dominik Sondej, Ryszard Szplet |
A combination of multi-edge coding and independent coding lines for time-to-digital conversion. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Kenneth M. Zick, Sen Li, Matthew French |
High-precision self-characterization for the LUT burn-in information leakage threat. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito |
A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Tuan D. A. Nguyen, Akash Kumar 0001 |
PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias |
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev |
Asynchronously assisted FPGA for variability. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Frederik Grüll, Udo Kebschull |
Biomedical image processing and reconstruction with dataflow computing on FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Abdulazim Amouri, Florent Bruguier, Saman Kiamehr, Pascal Benoit, Lionel Torres, Mehdi Baradaran Tahoori |
Aging effects in FPGAs: an experimental analysis. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez |
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christian Fobel, Gary William Grewal, Deborah Stacey |
A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hasan Azgin, Serkan Yaliman, Ilker Hamzaoglu |
A high performance alternating projections image demosaicing hardware. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright |
High level programming framework for FPGAs in the data center. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey, Sven Simon 0001 |
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ryan Marlow, Chris Dobson, Peter Athanas |
An enhanced and embedded GNU radio flow. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Athanasios Stratikopoulos, Grigorios Chrysos 0001, Ioannis Papaefstathiou, Apostolos Dollas |
HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Shyamsundar Venkataraman, Rui Santos, Anup Das 0001, Akash Kumar 0001 |
A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Garzia, Alexander Rügamer, Robert Koch 0002, Philipp Neumaier, Ekaterina Serezhkina, Matthias Overbeck, Günter Rohmer |
Experimental multi-FPGA GNSS receiver platform. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ali Ebrahim, Tughrul Arslan, Xabier Iturbe |
A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu |
Compiling text analytics queries to FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Zhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala |
FPGA implementation of low-power split-radix FFT processors. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Davor Capalija, Tarek S. Abdelrahman |
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Andrew Canis, Stephen Dean Brown, Jason Helge Anderson |
Modulo SDC scheduling with recurrence minimization in high-level synthesis. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk |
Automated framework for FPGA-based parallel genetic algorithms. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Eddie Hung, Tim Todman, Wayne Luk |
Transparent insertion of latency-oblivious logic onto FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero |
MAPC: Memory access pattern based controller. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Khalid Javeed, Xiaojun Wang 0001 |
Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura |
Caching memcached at reconfigurable network interface. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Cláudio Machado Diniz, Muhammad Shafique 0001, Sergio Bampi, Jörg Henkel |
Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hirak J. Kashyap, Ricardo Chaves |
Secure partial dynamic reconfiguration with unsecured external memory. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Chen Yang 0005, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao 0002, Shaojun Wei |
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Youkou Sogabe, Tsutomu Maruyama |
FPGA acceleration of short read mapping based on sort and parallel comparison. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar |
Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Siddhartha 0001, Nachiket Kapre |
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christian Beckhoff, Dirk Koch, Jim Tørresen |
Portable module relocation and bitstream compression for Xilinx FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides |
Area implications of memory partitioning for high-level synthesis on FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Pingfan Meng, Matthew Jacobsen, Motoki Kimura, Vladimir Dergachev, Thomas Anantharaman, Michael Requa, Ryan Kastner |
Hardware accelerated novel optical de novo assembly for large-scale genomes. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo |
An FPGA sliding window-based architecture harris corner detector. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Michael Kunz, Alexander Ostrowski, Peter Zipf |
An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Abhinav Agarwal, Haitham Hassanieh, Omid Abari, Ezzeldin Hamed, Dina Katabi, Arvind |
High-throughput implementation of a million-point sparse Fourier Transform. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Martin Kumm, Peter Zipf |
Pipelined compressor tree optimization using integer linear programming. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Vincent Mirian, Paul Chow |
Using an OpenCL framework to evaluate interconnect implementations on FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Toru Katagiri, Hideharu Amano |
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj |
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Thomas B. Preußer, Rainer G. Spallek |
Ready PCIe data streaming solutions for FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Mohamad Najem, Pascal Benoit, Florent Bruguier, Gilles Sassatelli, Lionel Torres |
Method for dynamic power monitoring on FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Pablo Leyva, Ginés Doménech-Asensi, F. Javier Garrigós, Julio Illade-Quinteiro, Víctor M. Brea 0001, Paula López 0001, Diego Cabello |
Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song 0002, John Mawer, Adrián Cristal, Mikel Luján |
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer |
The LEAP FPGA operating system. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin |
Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Arash Farhadi Beldachi, José L. Núñez-Yáñez |
Accurate power control and monitoring in ZYNQ boards. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jian Gong, Tao Wang 0004, Jiahua Chen, Haoyang Wu, Fan Ye 0003, Songwu Lu, Jason Cong |
An efficient and flexible host-FPGA PCIe communication library. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Oliver Knodel, Martin Zabel, Patrick Lehmann 0001, Rainer G. Spallek |
Educating hardware design - From primary school children to postgraduate engineers. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou |
FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Alexander Wild, Tim Güneysu |
Enabling SRAM-PUFs on Xilinx FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yanbiao Li, Dafang Zhang, Xian Yu, Wei Liang 0005, Jing Long, Hong Qiao |
Accelerate NDN name lookup using FPGA: Challenges and a scalable approach. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi |
RAM-based hardware accelerator for network data anonymization. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lin Gan, Haohuan Fu, Chao Yang 0002, Wayne Luk, Wei Xue, Oskar Mencer, Xiaomeng Huang, Guangwen Yang |
A highly-efficient and green data flow engine for solving euler atmospheric equations. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides |
FPGA implementation of an interior point method for high-speed model predictive control. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin, Wayne Luk |
Dataflow acceleration of Krylov subspace sparse banded problems. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Rui Santos, Shyamsundar Venkataraman, Anup Das 0001, Akash Kumar 0001 |
Criticality-aware scrubbing mechanism for SRAM-based FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christian Brugger, Christian de Schryver, Norbert Wehn |
HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ernesto Sánchez 0001, Luca Sterpone, Anees Ullah |
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Marcin Pietras |
Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | James J. Davis 0001, Peter Y. K. Cheung |
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Shane T. Fleming, David B. Thomas |
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne |
Hardware system synthesis from Domain-Specific Languages. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Adithya Pulli, Carlo Galuzzi, Georgi Gaydadjiev |
Towards domain-specific Instruction-Set Generation. |
FPL |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
Managing the FPGA memory wall: Custom computing or vector processing? |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Qian Zhao 0001, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
An automatic FPGA design and implementation framework. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Luiz G. A. Martins, Eduardo Marques |
Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
A spiking neural network on a portable FPGA tablet. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Matthew Jacobsen, Ryan Kastner |
RIFFA 2.0: A reusable integration framework for FPGA accelerators. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Arvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, Ramarathnam Venkatesan |
A secure coprocessor for database applications. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Kliem, Sven-Ole Voigt |
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | José M. Leitão, José A. Germano, Nuno Roma, Ricardo Chaves, Pedro Tomás |
Scalable and high throughput biosensing platform. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Bruno da Silva 0001, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire |
Comparing and combining GPU and FPGA accelerators in an image processing context. |
FPL |
2013 |
DBLP DOI BibTeX RDF |
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