Search results for "ISQED"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Wei Wang 0082	Automated Shmoo data analysis: A machine learning approach.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Manoj Singh Parihar	Realization of efficient RF energy harvesting circuits employing different matching technique.	ISQED	2014	DBLP DOI BibTeX RDF
1	Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi	Impact of FinFET technology for power gating in nano-scale design.	ISQED	2014	DBLP DOI BibTeX RDF
1	Peyman Pouyan, Esteve Amat, Enrique Barajas, Antonio Rubio 0001	Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches.	ISQED	2014	DBLP DOI BibTeX RDF
1	Jacob Murray, Paul Wettin, Ryan Gary Kim, Xinmin Yu, Partha Pratim Pande, Behrooz A. Shirazi, Deuk Hyoun Heo	Thermal hotspot reduction in mm-Wave wireless NoC architectures.	ISQED	2014	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Siddhartha Nath	Optimal reliability-constrained overdrive frequency selection in multicore systems.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab	Statistical methodology for modeling non-IID memory fails events.	ISQED	2014	DBLP DOI BibTeX RDF
1	Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi	Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits.	ISQED	2014	DBLP DOI BibTeX RDF
1	Kai-Hui Chang, Yen-Ting Liu, Chris Browy	Automated methods for eliminating X bugs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Dinesh Ganta, Leyla Nazhandali	Study of IC aging on ring oscillator physical unclonable functions.	ISQED	2014	DBLP DOI BibTeX RDF
1	Amir Momeni, Perhaad Mistry, David R. Kaeli	A parallel clustering algorithm for placement.	ISQED	2014	DBLP DOI BibTeX RDF
1	Chessda Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani	An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mukta Singh Parihar, Abhinav Kranti	Volume accumulated double gate junctionless MOSFETs for low power logic technology applications.	ISQED	2014	DBLP DOI BibTeX RDF
1	Anup Shrivastava, Jawar Singh	Dual-sided doped memristor and it's SPICE modelling for improved electrical properties.	ISQED	2014	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Hyein Lee 0001	Timing margin recovery with flexible flip-flop timing model.	ISQED	2014	DBLP DOI BibTeX RDF
1	Yijie Huangfu, Wei Zhang 0002	Compiler-directed leakage energy reduction for instruction scratch-pad memories.	ISQED	2014	DBLP DOI BibTeX RDF
1	Alexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel	Adding virtualization support in MIPS 4Kc-based MPSoCs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Jarbas Silveira, Paulo César Cortez, Giovanni Cordeiro Barroso, César A. M. Marcon	Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li 0002	NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Tomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera	Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mehrdad Khatir, Leyla Nazhandali	Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit.	ISQED	2014	DBLP DOI BibTeX RDF
1	Kamran Rahmani, Prabhat Mishra 0001, Sandip Ray	Efficient trace signal selection using augmentation and ILP techniques.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hu Chen, Sanghamitra Roy, Koushik Chakraborty	Exploiting static and dynamic locality of timing errors in robust L1 cache design.	ISQED	2014	DBLP DOI BibTeX RDF
1	Ming Fan 0001, Qiushi Han, Gang Quan, Shangping Ren	Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound.	ISQED	2014	DBLP DOI BibTeX RDF
1	Yanqing Zhang 0002, Benton H. Calhoun	Fast, accurate variation-aware path timing computation for sub-threshold circuits.	ISQED	2014	DBLP DOI BibTeX RDF
1	Jacqueline Woods, Sridhar Iyengar, Amit Sinha, Subhasish Mitra, Stacy Cannady	A new era of computing: Are you "ready now" to build a smarter and secured enterprise?	ISQED	2014	DBLP DOI BibTeX RDF
1	Eduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Moraes 0001	Runtime fault recovery protocol for NoC-based MPSoCs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Parag Kulkarni, Puneet Gupta 0001, Rudy Beraha	Minimizing clock domain crossing in Network on Chip interconnect.	ISQED	2014	DBLP DOI BibTeX RDF
1	Senthil Arasu, Mehrdad Nourani, Frank Cano, John M. Carulli, Vijay Reddy	Asymmetric aging of clock networks in power efficient designs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Arijit Banerjee 0002, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun	A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger	Protection of Muller-Pipelines from transient faults.	ISQED	2014	DBLP DOI BibTeX RDF
1	Di-An Li, Malgorzata Marek-Sadowska	Estimating true worst currents for power grid electromigration analysis.	ISQED	2014	DBLP DOI BibTeX RDF
1	Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Avoiding unnecessary write operations in STT-MRAM for low power implementation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mark Buckler, Wayne P. Burleson	Predictive synchronization for DVFS-enabled multi-processor systems.	ISQED	2014	DBLP DOI BibTeX RDF
1	Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid 0001	Measuring SET pulsewidths in logic gates using digital infrastructure.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark	Methodology to optimize critical node separation in hardened flip-flops.	ISQED	2014	DBLP DOI BibTeX RDF
1	Darshan Gandhi, Andreas Gerstlauer, Lizy K. John	FastSpot: Host-compiled thermal estimation for early design space exploration.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mitsuhiko Igarashi, Hideki Aono, Hideaki Abe, Koji Shibutani, Kan Takeuchi	Assessment of reliability impact on GHz processors with moderate overdrive.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sandeep Koranne	Constructing small-signal equivalent impedances using ellipsoidal norms.	ISQED	2014	DBLP DOI BibTeX RDF
1	Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu	On pattern generation for maximizing IR drop.	ISQED	2014	DBLP DOI BibTeX RDF
1	Vikram B. Suresh, Wayne P. Burleson	Fine grained wearout sensing using metastability resolution time.	ISQED	2014	DBLP DOI BibTeX RDF
1	Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Ilie I. Luican, Doru V. Nasui	Energy-aware scratch-pad memory partitioning for embedded systems.	ISQED	2014	DBLP DOI BibTeX RDF
1	Miroslav N. Velev, Ping Gao 0002	Formal verification of safety of polymorphic heterogeneous multi-core architectures.	ISQED	2014	DBLP DOI BibTeX RDF
1	Halil Kukner, Moustafa A. Khatib, Sebastien Morrison, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken	Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske	Delay and power optimization with TSV-aware 3D floorplanning.	ISQED	2014	DBLP DOI BibTeX RDF
1	Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz	Coverage of compositional property sets under reactive constraints.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sharayu Jagtap, Sivaramakrishna Rudrapati, Shalabh Gupta	Design of radiation hardened wide tuning range CMOS oscillators.	ISQED	2014	DBLP DOI BibTeX RDF
1	Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif	Statistical analysis of process variation induced SRAM electromigration degradation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sung S.-Y. Hsueh, Ryan H.-M. Huang, Charles H.-P. Wen	TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits.	ISQED	2014	DBLP DOI BibTeX RDF
1	Rafael M. Madeira, Edna Barros, Camila Ascendina	Towards more reliable embedded systems through a mechanism for monitoring driver devices communication.	ISQED	2014	DBLP DOI BibTeX RDF
1	Ying Zhang 0016, Lide Duan, Bin Li 0008, Lu Peng 0001, Sadagopan Srinivasan	Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors.	ISQED	2014	DBLP DOI BibTeX RDF
1		Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014	ISQED	2014	DBLP BibTeX RDF
1	Tiansong Cui, Shuang Chen 0001, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect.	ISQED	2014	DBLP DOI BibTeX RDF
1	Heesun Kim, Seungyun Sohn, Yoonjin Kim	Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture.	ISQED	2014	DBLP DOI BibTeX RDF
1	Harald Steiner, Wilfried Hortschitz, Franz Keplinger, Thilo Sauter	Topology optimization of a passive thermal actuator.	ISQED	2014	DBLP DOI BibTeX RDF
1	Xue Lin, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes.	ISQED	2014	DBLP DOI BibTeX RDF
1	Prasanjeet Das, Sandeep K. Gupta 0001	Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang	Concurrency-oriented SoC re-certification by reusing block-level test vectors.	ISQED	2014	DBLP DOI BibTeX RDF
1	Kartikeya Bhardwaj, Pravin S. Mane, Jörg Henkel	Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems.	ISQED	2014	DBLP DOI BibTeX RDF
1	Eman El Mandouh	Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools.	ISQED	2014	DBLP DOI BibTeX RDF
1	Tianyi Wang, Ming Fan 0001, Gang Quan, Shangping Ren	Heterogeneity exploration for peak temperature reduction on multi-core platforms.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii	Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS.	ISQED	2014	DBLP DOI BibTeX RDF
1	Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa	40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.	ISQED	2014	DBLP DOI BibTeX RDF
1	Ying-Chi Li, Sheldon X.-D. Tan, Tan Yu, Xin Huang 0003, Ngai Wong	Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie 0001	Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.	ISQED	2014	DBLP DOI BibTeX RDF
1	Varadan Savulimedu Veeravalli, Andreas Steininger	Architecture for monitoring SET propagation in 16-bit Sklansky adder.	ISQED	2014	DBLP DOI BibTeX RDF
1	Komal Singh, Chitrakant Sahu, Jawar Singh	Linearly separable pattern classification using memristive crossbar circuits.	ISQED	2014	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Rabie Ben Atitallah, Smaïl Niar	PETS: Power and energy estimation tool at system-level.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hyungjung Seo, Taewhan Kim	Post-silicon tunable clock buffer allocation based on fast chip yield computation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hasan Sohofi, Zainalabedin Navabi	Assertion-based verification for system-level designs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Mir Mohammad Navidi, Gyung-Su Byun	Comparative analysis of clock distribution networks for TSV-based 3D IC designs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	Specification and formal verification of power gating in processors.	ISQED	2014	DBLP DOI BibTeX RDF
1	Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee	3D-ICs with self-healing capability for thermal effects in RF circuits.	ISQED	2014	DBLP DOI BibTeX RDF
1	Shirish Bahirat, Sudeep Pasricha	HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures.	ISQED	2014	DBLP DOI BibTeX RDF
1	Chongxi Bao, Domenic Forte, Ankur Srivastava 0001	On application of one-class SVM to reverse engineering-based hardware Trojan detection.	ISQED	2014	DBLP DOI BibTeX RDF
1	Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.	ISQED	2014	DBLP DOI BibTeX RDF
1	Md. Abir Khan, Saraju P. Mohanty, Elias Kougianos	Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications.	ISQED	2014	DBLP DOI BibTeX RDF
1	Bo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez	Sub-threshold custom standard cell library validation.	ISQED	2014	DBLP DOI BibTeX RDF
1	Ting Chen, Xiaowei Pan, Hengzhu Liu, Tiebin Wu	Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0.	ISQED	2014	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Kriging bootstrapped neural network training for fast and accurate process variation analysis.	ISQED	2014	DBLP DOI BibTeX RDF
1	Jiyuan Luan, Michael DiVita	An integrated precision clock generator for implanted electronics with superior long-term stability.	ISQED	2014	DBLP DOI BibTeX RDF
1	Song Yao, Xiaoming Chen 0003, Yu Wang 0002, Yuchun Ma, Yuan Xie 0001, Huazhong Yang	Efficient region-aware P/G TSV planning for 3D ICs.	ISQED	2014	DBLP DOI BibTeX RDF
1	Tejasi Pimpalkhute, Sudeep Pasricha	An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors.	ISQED	2014	DBLP DOI BibTeX RDF
1	Abhishek A. Sinkar, Hao Wang 0011, Nam Sung Kim	Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores.	ISQED	2014	DBLP DOI BibTeX RDF
1	Yao Li 0009, Ramy Iskander, Marie-Minerve Louërat	Modeling, design and verification platform using SystemC AMS.	ISQED	2014	DBLP DOI BibTeX RDF
1	Sudhi Proch, Prabhat Mishra 0001	Directed test generation for hybrid systems.	ISQED	2014	DBLP DOI BibTeX RDF
1	Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans	Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design.	ISQED	2014	DBLP DOI BibTeX RDF
1	Seong-I Lei, Chris Chu, Wai-Kei Mak	Double patterning-aware detailed routing with mask usage balancing.	ISQED	2014	DBLP DOI BibTeX RDF
1	Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung	Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors.	ISQED	2014	DBLP DOI BibTeX RDF
1	Xue Lin, Yanzhi Wang, Massoud Pedram	Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime.	ISQED	2014	DBLP DOI BibTeX RDF
1	Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi	An analytical approach to system-level variation analysis and optimization for multi-core processor.	ISQED	2014	DBLP DOI BibTeX RDF
1	Kyungsu Kang, Giovanni De Micheli, Seunghan Lee, Chong-Min Kyung	Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache.	ISQED	2014	DBLP DOI BibTeX RDF
1	Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng	Relocatable and resizable SRAM synthesis for via configurable structured ASIC.	ISQED	2013	DBLP DOI BibTeX RDF
1	Noemie Beringuier-Boher, David Hély, Vincent Beroulle, Joel Damiens, Philippe Candelier	Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology.	ISQED	2013	DBLP DOI BibTeX RDF
1	Conor O'Sullivan, Peter M. Levine, Siddharth Garg	Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jordan Bisasky, Houman Homayoun, Farhang Yazdani, Tinoosh Mohsenin	A 64-core platform for biomedical signal processing.	ISQED	2013	DBLP DOI BibTeX RDF
1	Matthew Cotter, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan	Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications.	ISQED	2013	DBLP DOI BibTeX RDF
1	Richard Lee, Karim Abdel-Khalek, Samar Abdi, Frederic Risacher	Early system level modeling of real-time applications on embedded platforms.	ISQED	2013	DBLP DOI BibTeX RDF
1	Nozad Karim	New electrical design verification approach for 2.5D/3D package signal and power integrity.	ISQED	2013	DBLP DOI BibTeX RDF
1	Bahram N. Uchevler, Kjetil Svarstad, Jan Kuper, Christiaan Baaij	System-level modelling of dynamic reconfigurable designs using functional programming abstractions.	ISQED	2013	DBLP DOI BibTeX RDF

Publications at "ISQED"( http://dblp.L3S.de/Venues/ISQED )