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Results
Found 1972 publication records. Showing 1972 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Xinfei Guo, Mircea R. Stan |
Implications of accelerated self-healing as a key design knob for cross-layer resilience.  |
Integr.  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Milad Kaboli, Behzad Ghanavati, Majid Akhlaghi |
A new CMOS pseudo approximation exponential function generator by modified particle swarm optimization algorithm. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst |
Ensuring safety and efficiency in networks-on-chip. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Aijiao Cui, Yanhui Luo, Huawei Li 0001, Gang Qu 0001 |
Why current secure scan designs fail and how to fix them? |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Yasmin Afsharnezhad, Elham Zahraie Salehi |
CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Navid Rahmanikia, Amirali Amiri, Hamid Noori, Farhad Mehdipour |
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya |
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Can Baltaci, Yusuf Leblebici |
Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Rahati Belabad, Seyed Ahmad Motamedi, Saeed Sharifian |
An adaptive digital predistortion for compensating nonlinear distortions in RF power amplifier with memory effects. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Maryam Dehbashian, Mohammad Maymandi-Nejad |
A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert DiBiano, Supratik Mukhopadhyay |
Automated diagnostics for manufacturing machinery based on well-regularized deep neural networks. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Ashok Srivastava, Shiyan Hu, Prasun Ghosal |
Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Héctor Gómez, Óscar Reyes, Elkim Roa |
A 65 nm CMOS key establishment core based on tree parity machines. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jie He 0001, Liyuan Xu, Peng Wang 0020, Qin Wang 0004 |
A high precise E-nose for daily indoor air quality monitoring in living environment. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Sudeendra Kumar, G. Hanumanta Rao, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra |
Secure split test techniques to prevent IC piracy for IoT devices. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Carlos Aristoteles De la Cruz-Blas, G. Thomas-Erviti, José María Algueta-Miguel, Antonio J. López-Martín |
CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin |
Minimizing detection-to-boosting latency toward low-power error-resilient circuits. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Maura Casciola, Micaela Liberti, Agnese Denzi, Alessandra Paffi, Caterina Merla, Francesca Apollonio |
A computational design of a versatile microchamber for in vitro nanosecond pulsed electric fields experiments. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Giulia Di Capua, Nicola Femia, Kateryna Stoyka |
A generalized numerical method for ferrite inductors analysis in high current ripple operation. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Deokjin Joo, Taewhan Kim |
Clock buffer polarity assignment under useful skew constraints. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy 0001, Ranjani Narayan |
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Jin 0004, Guanghui He, Weifeng He, Zhigang Mao |
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail |
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick W. C. Ho, Haider Abbas F. Almurib, T. Nandha Kumar |
Configurable memristive logic block for memristive-based FPGA architectures. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra |
A novel current controlled configurable RO PUF with improved security metrics. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Maryam Dehbashian, Mohammad Maymandi-Nejad |
Co-AGSA: An efficient self-adaptive approach for constrained optimization of analog IC based on the shrinking circles technique. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Shaoming Chen, Saraju P. Mohanty |
A novel switchable pin method for regulating power in chip-multiprocessor. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Zhang, Rostislav (Reuven) Dobkin, Aharon Unikovski, Danniel Nahmanny, Goel Samuel, Michael Moyal, Ran Ginosar |
A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Travis Meade, Shaojie Zhang, Yier Jin |
IP protection through gate-level netlist security enhancement. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören 0001, H. Fatih Ugurdag |
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gunti Nagendra Babu, Karthikeyan Lingasubramanian |
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler |
Synthesis of optical circuits using binary decision diagrams. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis |
Jitter tolerance calibration for high-speed serial interfaces. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajit Karmakar, Santanu Chattopadhyay |
Temperature and data size trade-off in dictionary based test data compression. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zbigniew Hajduk |
Simple method of asynchronous circuits implementation in commercial FPGAs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahya Sam Daliri, Reza Faghih Mirzaee, Keivan Navi, Nader Bagherzadeh |
High-performance ternary operators for scrambling. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuan Xue, Chengmo Yang |
Path reuse-aware routing for non-volatile memory based FPGAs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan |
An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wazir Singh, Ankita Shukla, Sujay Deb, Angshul Majumdar |
Energy efficient EEG acquisition and reconstruction for a Wireless Body Area Network. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zongwei Li, Xingyin Xiong, Xiong Liu, Kedu Han, Ning Cong, Changchun Yang |
Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | George K. Papakonstantinou |
Exclusive or Sum of Complex Terms expressions minimization. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Siraj Fulum Mossa, Syed Rafay Hasan, Omar S. Elkeelany |
Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Liu, Hui Guo 0001, Sri Parameswaran, Xiaobo Sharon Hu |
iCETD: An improved tag generation design for memory data authentication in embedded processor systems. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Behnam Khodabandeloo, Ahmad Khonsari, Masoomeh Jasemi, Golnaz Taheri |
A fast temperature-aware fixed-outline floorplanning framework using convex optimization. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lu Wang 0019, Sheng Ma, Chen Li 0015, Wei Chen 0009, Zhiying Wang 0003 |
A high performance reliable NoC router. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jubin Mitra, Tapan Kumar Nayak |
Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongmei Chen 0005, Yunsheng Pan, Yongsheng Yin, Fujiang Lin |
All-digital background calibration technique for timing mismatch of time-interleaved ADCs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis Koutras, Konstantinos Maragos 0001, Dionysios Diamantopoulos, Kostas Siozios, Dimitrios Soudris |
On supporting rapid prototyping of embedded systems with reconfigurable architectures. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Joohan Kim, Taewhan Kim |
Boundary optimization of buffered clock trees for low power. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan Frey, Qiaoyan Yu |
A hardened network-on-chip design using runtime hardware Trojan mitigation methods. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hengfei Zhong, Zhuoquan Huang, Dihu Chen, Tao Su, Zixin Wang |
A mechanism for detecting on-chip radio frequency interference of field-programmable gate array. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jie Jin |
Resonant amplifier-based sub-harmonic mixer for zero-IF transceiver applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitar Nikolov, Erik Larsson |
Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeyoung Kim, Pinaki Mazumder |
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Samin Ebrahim Sorkhabi, Lihong Zhang |
Automated topology synthesis of analog and RF integrated circuits: A survey. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi |
Hardware design of LIF with Latency neuron model with memristive STDP synapses. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hadi Ghasemzadeh Momen, Metin Yazgi, Ramazan Köprü, Ali Naderi Saatlo |
Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Libao Deng, Baoquan Zhang, Sha Wang, Chengyu Jin |
IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyoungseok Moon, Taewhan Kim |
Loosely coupled multi-bit flip-flop allocation for power reduction. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anu Tonk, Neelofer Afzal |
On advance towards sub-sampling technique in phase locked loops - A review. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qi Xu, Song Chen 0001 |
Fast thermal analysis for fixed-outline 3D floorplanning. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Maede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Hung Hsieh, Jian-Hao Huang, Hung-Ren Wang |
DVFS-aware motion estimation design scheme based on bandwidth-rate-distortion optimization in application processor systems. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan |
A novel test compression algorithm for analog circuits to decrease production costs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | H. C. Bandala-Hernandez, Alejandro Díaz-Sánchez, José Miguel Rocha-Pérez, Jaime Ramírez-Angulo, I. Y. López-Ortega, Javier Lemus-López, Jesús Ezequiel Molinar-Solís |
CMOS Analog Rank Order Filters using positive feedback comparators. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lorenzo Iotti, Matteo Bassi, Andrea Mazzanti, Francesco Svelto |
Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Jin 0004, Weifeng He, Jianfei Jiang 0001, Haichao Huang, Xuejun Zhao, Yanan Sun 0003, Xin Chen, Naifeng Jing |
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Nuno Horta, Andrea Baschirotto, Francisco V. Fernández 0001, Günhan Dündar, João Goes, Jorge Fernandes |
Introduction to the special issue on PRIME 2016 and SMACD 2016. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jenny Klaus, Eric Schaefer, Roman Paris, Astrid Frank, Ralf Sommer |
A contribution towards model-based design of application-specific MEMS. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | He Tang, Yong Peng, Xiang Lu, Albert Z. Wang, Hai Wang 0002 |
A quantitative design methodology for high-speed interpolation/averaging ADCs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qin Wang 0009, Zhenyang Chen, Jianfei Jiang 0001, Zheng Guo 0001, Zhigang Mao |
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Masumeh Damghanian, Seyed Javad Azhari |
A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu |
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Engin Afacan, Günhan Dündar, Ali Emre Pusane, Mustafa Berke Yelten, I. Faik Baskaya |
Aging signature properties and an efficient signature determination tool for online monitoring. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gian Domenico Licciardo, Thomas Boesch, Danilo Pau, Luigi Di Benedetto |
Frame buffer-less stream processor for accurate real-time interest point detection. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hashem Haghbayan, Bijan Alizadeh |
A dynamic specification to automatically debug and correct various divider circuits. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin |
Wakeup scheduling and its buffered tree synthesis for power gating circuits. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rafaella Fiorelli, Eduardo J. Peralías |
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen |
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Mendonça dos Santos, Luís Mendes, João Caldinhas Vaz |
Substrate noise isolation improvement in a single-well standard CMOS process. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço 0003, Nuno Horta |
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin Sun 0006, Liang Xiao 0001, Jiangshan Tian, He Zhou, Janet Roveda |
Surrogating circuit design solutions with robustness metrics. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui |
BiLink: A high performance NoC router architecture using bi-directional link with double data rate. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Juyeon Kim, Deokjin Joo, Taewhan Kim |
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Nuno Lourenço 0003, Ricardo Martins 0003, António Canelas, Ricardo Povoa, Nuno Horta |
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Murat Pak, Francisco V. Fernández 0001, Günhan Dündar |
Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai He, Sheldon X.-D. Tan, Hengyang Zhao, Xuexin Liu, Hai Wang 0002, Guoyong Shi |
Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander E. Shapiro, Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, Eby G. Friedman |
Adaptive power gating of 32-bit Kogge Stone adder. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yishai Statter, Tom Chen 0001 |
A novel high-throughput method for table look-up based analog design automation. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita |
An efficient tool for the assisted design of SAR ADCs capacitive DACs. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amin Sallem, Pedro Pereira 0001, M. Helena Fino, Mourad Fakhfakh |
A hybrid approach for the sensitivity analysis of integrated inductors. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Julia Funke, Stefan Hougardy, Jan Schneider 0002 |
An exact algorithm for wirelength optimal placements in VLSI design. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Engin Afacan, Gönenç Berkol, Günhan Dündar, Ali Emre Pusane, I. Faik Baskaya |
A lifetime-aware analog circuit sizing tool. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone |
UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Geng, Jianming Liu 0001, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi 0001 |
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Farshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Bin Abd Manaf |
Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon |
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Elisenda Roca, Javier J. Sieiro |
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Albeck, Shmuel Wimer |
Energy efficient computing by multi-mode addition. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | He Li, Qiang Liu 0011, Jiliang Zhang 0002 |
A survey of hardware Trojan threat and defense. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
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