Search results for "Microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook	A circuit level implementation of an adaptive issue queue for power-aware microprocessors.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
14	Miroslav N. Velev, Randal E. Bryant	Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors.	DAC	2001	DBLP DOI BibTeX RDF
14	Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin	Scalable Hybrid Verification of Complex Microprocessors.	DAC	2001	DBLP DOI BibTeX RDF
14	Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.	VLSI-SOC	2001	DBLP BibTeX RDF
14	Ing-Jer Huang, Wen-Fu Kao	A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors.	Des. Autom. Embed. Syst.	2000	DBLP DOI BibTeX RDF
14	Manfred Schlett	Embedded microprocessors: Evolution, trends and challenges.	Adv. Comput.	2000	DBLP DOI BibTeX RDF
14	Ken Sakamura	21st-Century Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
14	Chris Herring	Microprocessors, Microcontrollers, and Systems in the New Millennium.	IEEE Micro	2000	DBLP DOI BibTeX RDF
14	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George I. Stamoulis	Architectural and compiler techniques for energy reduction in high-performance microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
14	Jurij Silc, Theo Ungerer, Borut Robic	A survey of new research directions in microprocessors.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
14	Torbjørn Rognes, Erling Seeberg	Six-fold speed-up of Smith-Waterman sequence database searches using parallel processing on common microprocessors.	Bioinform.	2000	DBLP DOI BibTeX RDF
14	Hemant G. Rotithor	Postsilicon Validation Methodology for Microprocessors.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
14	Miroslav N. Velev	Formal Verification of VLIW Microprocessors with Speculative Execution.	CAV	2000	DBLP DOI BibTeX RDF
14	Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man	Flexible hardware acceleration for multimedia oriented microprocessors.	MICRO	2000	DBLP DOI BibTeX RDF
14	Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus	A new method for on-line state machine observation for embedded microprocessors.	HLDVT	2000	DBLP DOI BibTeX RDF
14	David Ofelt, John L. Hennessy	Efficient performance prediction for modern microprocessors.	SIGMETRICS	2000	DBLP DOI BibTeX RDF
14	Yale N. Patt	Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve?	EUROMICRO	2000	DBLP DOI BibTeX RDF
14	Shervin Hojat, Paul Kartschoke	Techniques for Improving Timing Convergence of Advanced Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
14	Tamás Roska, Ángel Rodríguez-Vázquez	Review of CMOS implementations of the CNN universal machine-type visual microprocessors.	ISCAS	2000	DBLP DOI BibTeX RDF
14	Travis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao	Optical interferometric probing of advanced microprocessors.	ITC	2000	DBLP DOI BibTeX RDF
14	Pradip Bose, Jacob A. Abraham	Performance and Functional Verification of Microprocessors.	VLSI Design	2000	DBLP DOI BibTeX RDF
14	Gang Qu 0001, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak	Function-level power estimation methodology for microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
14	David W. Boerstler	A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
14	Jack Choquette, Mayank Gupta, Dominic McCarthy, Jack Veenstra	High performance RISC microprocessors.	IEEE Micro	1999	DBLP DOI BibTeX RDF
14	Mark A. Check, Timothy J. Slegel	Custom S/390 G5 and G6 microprocessors.	IBM J. Res. Dev.	1999	DBLP DOI BibTeX RDF
14	Robert M. Averill III, Keith G. Barkley, Michael A. Bowen, Peter J. Camporese, Allan H. Dansky, Robert F. Hatch, Dale E. Hoffman, Mark D. Mayo, Scott A. McCabe, Timothy G. McNamara, Thomas J. McPherson, Gregory A. Northrop, Leon J. Sigal, Howard H. Smith, David A. Webber, Patrick M. Williams	Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors.	IBM J. Res. Dev.	1999	DBLP DOI BibTeX RDF
14	G. Wang, Danesh K. Tafti	Performance Enhancement on Microprocessors with Hierarchical Memory Systems for Solving Large Sparse Linear Systems.	Int. J. High Perform. Comput. Appl.	1999	DBLP DOI BibTeX RDF
14	J. Giridhar, K. M. M. Prabhu	Erratum to "Implementation of MTD-WVD on a TMS320C30 DSP processor": [J. Microprocessors Microsyst. 22 (1998) 1-12].	Microprocess. Microsystems	1999	DBLP DOI BibTeX RDF
14	Jaime C. Fonseca 0001, João Luiz Afonso, Júlio S. Martins, Carlos Couto	Erratum to "Fuzzy logic speed control of an induction motor": [J. Microprocessors Microsyst. 22 (1999) 523-534].	Microprocess. Microsystems	1999	DBLP DOI BibTeX RDF
14	Jurij Silc, Borut Robic	Asynchronous Microprocessors.	Informatica (Slovenia)	1999	DBLP BibTeX RDF
14	Lee Lloyd, Keith Heron, Albert Koelmans, Alexandre Yakovlev	Asynchronous microprocessors: From high level model to FPGA implementation.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
14	Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki	Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
14	S. Deuty, C. S. Mitter	Transistor paradigm shift required to meet the power demands for microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
14	Alan Pita, Nadeem Malik	Sectored renaming for superscalar microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
14	Daniel A. Connors, Jean-Michel Puiatti, David I. August, Kevin M. Crozier, Wen-mei W. Hwu	An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors.	Euro-Par	1999	DBLP DOI BibTeX RDF
14	Pradip Bose	Performance Evaluation and Validation of Microprocessors.	SIGMETRICS	1999	DBLP DOI BibTeX RDF	performance evaluation, validation, processor design
14	Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-Lin Wu	Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology.	ICECS	1999	DBLP DOI BibTeX RDF
14	Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek	Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic.	IPPS/SPDP Workshops	1999	DBLP DOI BibTeX RDF
14	Byron Cook, John Launchbury, John Matthews, Richard B. Kieburtz	Formal Verification of Explicitly Parallel Microprocessors.	CHARME	1999	DBLP DOI BibTeX RDF
14	Thomas Lundqvist, Per Stenström	Timing Anomalies in Dynamically Scheduled Microprocessors.	RTSS	1999	DBLP DOI BibTeX RDF	timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor
14	Omar Hammami	Neural Network Classifiers Execution on Superscalar Microprocessors.	ISHPC	1999	DBLP DOI BibTeX RDF
14	Magdy S. Abadir, Rajesh Raina	Design-for-test methodology for Motorola PowerPC microprocessors.	ITC	1999	DBLP DOI BibTeX RDF
14	Li-C. Wang, Magdy S. Abadir	Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.	ITC	1999	DBLP DOI BibTeX RDF
14	Anjali Kinra	Towards reducing "functional only" fails for the UltraSPARC microprocessors.	ITC	1999	DBLP DOI BibTeX RDF
14	Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran	The testability features of the 3rd generation ColdFire family of microprocessors.	ITC	1999	DBLP DOI BibTeX RDF
14	Richard Raimi, Jacob A. Abraham	Detecting False Timing Paths: Experiments on PowerPC Microprocessors.	DAC	1999	DBLP DOI BibTeX RDF
14	Miroslav N. Velev, Randal E. Bryant	Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors.	DAC	1999	DBLP DOI BibTeX RDF
14	David Van Campenhout	Functional design verification for microprocessors by error modeling.		1999	RDF
14	Nikolaos Bellas	Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors		1999	RDF
14	Derek Chiou	Extending the reach of microprocessors: column and curious caching.		1999	RDF
14	Anthony C. J. Fox	Algebraic models for advanced microprocessors.		1999	RDF
14	Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang	Code Optimization Techniques in Embedded DSP Microprocessors.	Des. Autom. Embed. Syst.	1998	DBLP DOI BibTeX RDF
14	Bruce L. Jacob, Trevor N. Mudge	Virtual memory in contemporary microprocessors.	IEEE Micro	1998	DBLP DOI BibTeX RDF
14	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
14	Chris Basoglu, Donglok Kim, Robert J. Gove, Yongmin Kim 0001	High-performance image computing with modern microprocessors.	Int. J. Imaging Syst. Technol.	1998	DBLP DOI BibTeX RDF
14	David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown	High-level design verification of microprocessors via error modeling.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	design verification, error modeling, design errors
14	Mark Bohr	Silicon Trends and Limits for Advanced Microprocessors.	Commun. ACM	1998	DBLP DOI BibTeX RDF
14	Dale Amason, Alfred L. Crouch, Renny Eisele, Grady Giles, Michael Mateja	Test Development for Second-Generation ColdFire Microprocessors.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
14	Corinna G. Lee, Mark G. Stoodley	Simple Vector Microprocessors for Multimedia Applications.	MICRO	1998	DBLP DOI BibTeX RDF
14	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors.	MICRO	1998	DBLP DOI BibTeX RDF
14	Miroslav N. Velev, Randal E. Bryant	Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation.	ACSD	1998	DBLP DOI BibTeX RDF	pipelined microprocessor verification, memory shadowing, Efficient Memory Model (EMM), circuit correspondence checking, symbolic simulation
14	Csaba Andras Moritz, Donald Yeung, Anant Agarwal	Exploring Optimal Cost-Performance Designs for Raw Microprocessors.	FCCM	1998	DBLP DOI BibTeX RDF
14	S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann	Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors.	ICPADS	1998	DBLP DOI BibTeX RDF
14	Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos	Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.	ISLPED	1998	DBLP DOI BibTeX RDF
14	Simon Segars	The ARM9 family-high performance microprocessors for embedded applications.	ICCD	1998	DBLP DOI BibTeX RDF
14	Rolf Hakenes, Yiannos Manoli	The Microcore development system: a unified environment for designing new microprocessors.	ICCD	1998	DBLP DOI BibTeX RDF
14	Arun Chandra, Li-C. Wang, Magdy S. Abadir	Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
14	Pradip Bose	Performance Test Case Generation for Microprocessors.	VTS	1998	DBLP DOI BibTeX RDF
14	Miroslav N. Velev, Randal E. Bryant	Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking.	FMCAD	1998	DBLP DOI BibTeX RDF
14	Anjali Kinra, Aswin Mehta, Neal Smith, Jackie Mitchell, Fred Valente	Diagnostic techniques for the UltraSPARC microprocessors.	ITC	1998	DBLP DOI BibTeX RDF
14	Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez	Reducing Power in High-Performance Microprocessors.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
14	Richard W. Earnshaw, Lee D. Smith, Kevin Welton	Challenges in cross-development [single chip microprocessors].	IEEE Micro	1997	DBLP DOI BibTeX RDF
14	Peter A. Sandon, Yu-Chung Liao, Thomas E. Cook, David M. Schultz, Pedro Martin-de-Nicolas	NStrace: A bus-driven instruction trace tool for PowerPC microprocessors.	IBM J. Res. Dev.	1997	DBLP DOI BibTeX RDF
14	Kenneth L. Shepard, Sean M. Carey, Ee Kin Cho, Brian W. Curran, Robert F. Hatch, Dale E. Hoffman, Scott A. McCabe, Gregory A. Northrop, A. E. (Rick) Seigler	Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors.	IBM J. Res. Dev.	1997	DBLP DOI BibTeX RDF
14	Joon-Seo Yim, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung	Design Verification of Complex Microprocessors.	J. Circuits Syst. Comput.	1997	DBLP DOI BibTeX RDF
14	Marc E. Levitt	Guest Editor's Introduction: Microprocessors Lead the Way in Complex Design.	IEEE Des. Test Comput.	1997	DBLP BibTeX RDF
14	Sunil Kakkar	A comprehensive diagnostics software strategy for IDT's microprocessors.	COMPCON	1997	DBLP DOI BibTeX RDF
14	Hector Sanchez, Belli Kuttanna, Tim Olson, Mike Alexander, Gianfranco Gerosa, Ross Philip, Jose Alvarez	Thermal management system for high performance PowerPC™ microprocessors.	COMPCON	1997	DBLP DOI BibTeX RDF
14	Chris Basoglu, Yongmin Kim 0001	Real-time algorithm for generating color Doppler ultrasound images on commercially available microprocessors.	Medical Imaging: Image Processing	1997	DBLP DOI BibTeX RDF
14	Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung	Verification methodology of compatible microprocessors.	ASP-DAC	1997	DBLP DOI BibTeX RDF
14	Jeffrey L. Burns, Jack A. Feldman	C5M - a control logic layout synthesis system for high-performance microprocessors.	ISPD	1997	DBLP DOI BibTeX RDF
14	Randal E. Bryant, Miroslav N. Velev	Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation.	ASIAN	1997	DBLP DOI BibTeX RDF
14	Jeremy R. Levitt, Kunle Olukotun	Verifying correct pipeline implementation for microprocessors.	ICCAD	1997	DBLP DOI BibTeX RDF
14	Charles Roth, Jon Tyler, Paul Jagodik, Huy Nguyen	Divide and conquer approach to functional verification of PowerPC TM microprocessors.	IEEE International Workshop on Rapid System Prototyping	1997	DBLP DOI BibTeX RDF
14	Shervin Hojat, Paul Villarrubia	An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors.	ICCD	1997	DBLP DOI BibTeX RDF
14	Daniel W. Dobberpuhl	Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors.	ARVLSI	1997	DBLP DOI BibTeX RDF
14	Michael Mateja, Alfred L. Crouch, Renny Eisele, Grady Giles, Dale Amason	A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors.	ITC	1997	DBLP DOI BibTeX RDF
14	William J. Grundmann, Dan Dobberpuhl, Randy L. Allmon, Nicholas L. Rethman	Designing High Performance CMOS Microprocessors Using Full Custom Techniques.	DAC	1997	DBLP DOI BibTeX RDF
14	Ricardo Gonzalez, Mark Horowitz	Energy dissipation in general purpose microprocessors.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
14	Richard Mateosian	Microprocessors at 25.	IEEE Micro	1996	DBLP DOI BibTeX RDF
14	Albert Y. C. Yu	The future of microprocessors.	IEEE Micro	1996	DBLP DOI BibTeX RDF
14	Neal A. Harman, John V. Tucker	Algebraic Models of Microprocessors: Architecture and Organisation.	Acta Informatica	1996	DBLP DOI BibTeX RDF
14	Henk D. L. Hollmann, Jean-Paul M. G. Linnartz, Jacobus H. van Lint, C. P. M. J. Baggen	Protection of Software Algorithms Executed on Secure Microprocessors.	CARDIS	1996	DBLP BibTeX RDF
14	Steven Wallace, Nader Bagherzadeh	Instruction Fetching Mechanisms for Superscalar Microprocessors.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
14	David A. Clark, Brad L. Hutchings	Supporting FPGA microprocessors through retargetable software tools.	FCCM	1996	DBLP DOI BibTeX RDF
14	Jose Alvarez, Hector Sanchez, Roger Countryman, Mike Alexander, Carmine Nicoletta, Gianfranco Gerosa	A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors.	ICCD	1996	DBLP DOI BibTeX RDF
14	Anthony C. J. Fox, Neal A. Harman	An Algebraic Model of Correctness for Superscalar Microprocessors.	FMCAD	1996	DBLP DOI BibTeX RDF
14	Bishop Brock, Matt Kaufmann, J Strother Moore	ACL2 Theorems About Commercial Microprocessors.	FMCAD	1996	DBLP DOI BibTeX RDF
14	Wayne M. Needham, Naga Gollakota	DFT Strategy for Intel Microprocessors.	ITC	1996	DBLP DOI BibTeX RDF
14	Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas	Code Generation and Analysis for the Functional Verification of Microprocessors.	DAC	1996	DBLP DOI BibTeX RDF