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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han 0003, Xiaoyang Zeng, Xu Cheng 0002 |
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 116, pp. 105219, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Weizhen Wang, Jun Han 0003, Xu Cheng 0002, Xiaoyang Zeng |
An energy-efficient crypto-extension design for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 115, pp. 105165, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Imad Al Assir, Mohamad El Iskandarani, Hadi Rayan Al Sandid, Mazen A. R. Saghir |
Arrow: A RISC-V Vector Accelerator for Machine Learning Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.07169, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim |
Supporting CUDA for an extended RISC-V GPU architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2109.00673, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Asmit De, Swaroop Ghosh |
HeapSafe: Securing Unprotected Heaps in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.08712, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Andrew Wright, Adam Chlipala |
A Multipurpose Formal RISC-V Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.00762, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Flavia Caforio, Pierpaolo Iannicelli, Michele Paolino, Daniel Raho |
VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.02821, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Tao Lu |
A Survey on RISC-V Security: Hardware and Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.04175, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Bruno Sá, José Martins, Sandro Pinto 0001 |
A First Look at RISC-V Virtualization from an Embedded Systems Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.14951, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee |
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.07584, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Carlton Shepherd, Konstantinos Markantonakis, Georges-Axel Jaloyan |
LIRA-V: Lightweight Remote Attestation for Constrained RISC-V Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2102.08804, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Stefan Steinegger, David Schrammel, Samuel Weiser, Pascal Nasahl, Stefan Mangard |
SERVAS! Secure Enclaves via RISC-V Authenticryption Shield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.03395, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto 0001 |
PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.15286, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers |
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2101.05591, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Avani Dave, Nilanjan Banerjee, Chintan Patel |
CARE: Lightweight Attack Resilient Secure Boot Architecturewith Onboard Recovery for RISC-V based SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2101.06300, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Joao Mario Domingos, Pedro Tomás, Leonel Sousa |
Supporting RISC-V Performance Counters through Performance analysis tools for Linux (Perf). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2112.11767, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Georges-Axel Jaloyan, Konstantinos Markantonakis, Raja Naeem Akram, David Robin, Keith Mayes, David Naccache |
Return-Oriented Programming on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.08229, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Odysseas Chatzopoulos, George-Marios Fragkoulis, George Papadimitriou 0001, Dimitris Gizopoulos |
Towards Accurate Performance Modeling of RISC-V Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.09991, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Cristóbal Ramírez Lazo, César-Alejandro Hernández-Calderón, Oscar Palomar, Osman Sabri Unsal, Marco Antonio Ramírez, Adrián Cristal |
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.01949, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Blaise Tine, Fares Elsabbagh, Krishna Praveen Yalamarthy, Hyesoon Kim |
Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.10857, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.07456, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Mahya Morid Ahmadi, Faiq Khalid, Muhammad Shafique 0001 |
Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.08877, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone |
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Aerosp. Inf. Syst. ![In: J. Aerosp. Inf. Syst. 18(8), pp. 553-570, August 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf |
The design of scalar AES Instruction Set Extensions for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(1), pp. 109-136, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alexandre Adomnicai, Thomas Peyrin |
Fixslicing AES-like Ciphers New bitsliced AES speed records on ARM-Cortex M and RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(1), pp. 402-425, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jipeng Zhang, Junhao Huang, Zhe Liu 0001, Sujoy Sinha Roy |
Time-memory Trade-offs for Saber+ on Memory-constrained RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 1552, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
13 | Ben Marshall, Daniel Page, Thinh Hung Pham |
A lightweight ISE for ChaCha on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 1030, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Hwajeong Seo, Hyeokdong Kwon, Siwoo Eum, Kyungbae Jang, Hyunjun Kim, Hyunji Kim, Minjoo Sim, Gyeongju Song, Wai-Kong Lee |
All the Polynomial Multiplication You Need on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 1117, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
13 | Rami Elkhatib, Reza Azarderakhsh, Mehran Mozaffari Kermani |
Accelerated RISC-V for Post-Quantum SIKE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 597, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
13 | Huimin Li 0004, Nele Mentens, Stjepan Picek |
A Scalable SIMD RISC-V based Processor with Customized Vector Extensions for CRYSTALS-Kyber. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 1648, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Haifeng Zhang 0010, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang, Shengbing Zhang |
A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 21(19), pp. 6491, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Shiwei Yuan, Lei Li, Ji Yang, Yuanhang He, Wanting Zhou, Jin Li |
Real-time detection of hardware trojan attacks on General-Purpose Registers in a RISC-V processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 18(10), pp. 20210098, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Xuan-Tu Tran, Cong-Kha Pham |
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 18(16), pp. 20210266, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler |
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 116, pp. 102135, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Cong-Kha Pham |
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCS ![In: IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021, pp. 1-13, 2021, IEEE, 978-1-6654-1397-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Todd M. Austin, Austin Harris 0001, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari |
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCS ![In: IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021, pp. 1-18, 2021, IEEE, 978-1-6654-1397-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau |
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCS ![In: IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021, pp. 1-23, 2021, IEEE, 978-1-6654-1397-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Christoph Spang 0001, Florian Meisel, Andreas Koch 0001 |
RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings, pp. 179-194, 2021, Springer, 978-3-031-04579-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini |
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings, pp. 16-32, 2021, Springer, 978-3-031-04579-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Yi-Wen Hung, Yao-Tse Chang, Shuenn-Yuh Lee, Chou-Ching K. Lin, Gia-Shing Shieh |
An Energy-efficient and Programmable RISC-V CNN Coprocessor for Real-time Epilepsy Detection and Identification on Wearable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-TW ![In: IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021, Penghu, Taiwan, September 15-17, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-3328-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Fearghal Morgan, Arthur Beretta, Ian Gallivan, Joseph Clancy, Frédéric Rousseau 0001, Roshan George, László Bakó, Frank Callaly |
RISC-V Online Tutor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
REV ![In: Online Engineering and Society 4.0 - Proceedings of the 18th International Conference on Remote Engineering and Virtual Instrumentation, REV 2021, Hongkong, China, 24-26 February 2021., pp. 131-143, 2021, Springer, 978-3-030-82528-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sarah Hesham, Mohamed Shalan, M. Watheq El-Kharashi, Mohamed Dessouky |
Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021, pp. 498-502, 2021, IEEE, 978-1-6654-2461-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Michael Platzer, Peter P. Puschner |
Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 33rd Euromicro Conference on Real-Time Systems, ECRTS 2021, July 5-9, 2021, Virtual Conference., pp. 1:1-1:18, 2021, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-192-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad Ahmed, Hala Ibrahim, Hassan Mostafa |
Implementation and Functional Verification of RISC-V Core for Secure IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, December 19-22, 2021, pp. 254-257, 2021, IEEE, 978-1-6654-0839-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler |
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, Ahmad-Reza Sadeghi |
In Hardware We Trust? From TPM to Enclave Computing on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi |
AFTAB: A RISC-V Implementation with Configurable Gateways for Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: IEEE East-West Design & Test Symposium, EWDTS 2021, Batumi, Georgia, September 10-13, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-4503-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Abdelrahman Sobeih Hussein, Hassan Mostafa |
ASIC-FPGA Gap for a RISC-V Core Implementation for DNN Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NILES ![In: 3rd Novel Intelligent and Leading Emerging Sciences Conference, NILES 2021, Giza, Egypt, October 23-25, 2021, pp. 385-388, 2021, IEEE, 978-1-6654-2157-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Boria Pérez, Alexander Fell, John D. Davis |
Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 130-135, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Marouene Boubakri, Fausto Chiatante, Belhassen Zouari |
Towards a firmware TPM on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 647-650, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser |
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 627-632, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Robert Balas, Luca Benini |
RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 874-877, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi |
SealPK: Sealable Protection Keys for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1278-1281, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger |
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 325-332, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Muhammad Ali 0010, Matthias von Ameln, Diana Goehringer |
Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 30-34, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Gianluca Bellocchi, Alessandro Capotondi, Francesco Conti 0001, Andrea Marongiu |
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 9-17, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson |
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 35-42, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar |
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 557-561, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Vasileios Tsoutsouras, Orestis Kaparounakis, Bilgesu Arif Bilgin, Chatura Samarakoon, James Timothy Meech, Jan Heck, Phillip Stanley-Marbell |
The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021, pp. 1254-1269, 2021, ACM, 978-1-4503-8557-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Haonan Li 0009, Weijie Huang, Mingde Ren, Hongyi Lu, Zhenyu Ning, Heming Cui, Fengwei Zhang |
A Novel Memory Management for RISC-V Enclaves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASP@MICRO ![In: HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, Virtual Event, 18 October 2021, pp. 3:1-3:9, 2021, ACM, 978-1-4503-9614-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim |
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021, pp. 754-766, 2021, ACM, 978-1-4503-8557-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Evelina Forno, Andrea Spitale, Enrico Macii, Gianvito Urgese |
Configuring an Embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge Computing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021, pp. 328-332, 2021, IEEE, 978-1-6654-3860-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Risikesh RK, Sharad Sinha, Nanditha P. Rao |
Variable Bit-Precision Vector Extension for RISC-V Based Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021, pp. 114-121, 2021, IEEE, 978-1-6654-3860-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Takuto Kanamori, Kenji Kise |
RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021, pp. 38-45, 2021, IEEE, 978-1-6654-3860-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Md. Ashraful Islam, Kenji Kise |
Efficient Resource Shared RISC-V Multicore Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021, pp. 366-372, 2021, IEEE, 978-1-6654-3860-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jaume Abella 0001, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker 0001, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández 0001, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer 0002, Stefan Wagner 0001, Francesco Regazzoni 0001 |
Security, Reliability and Test Aspects of the RISC-V Ecosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 26th IEEE European Test Symposium, ETS 2021, Bruges, Belgium, May 24-28, 2021, pp. 1-10, 2021, IEEE, 978-1-6654-1849-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ramon Wirsch, Christian Hochberger |
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings, pp. 118-132, 2021, Springer, 978-3-030-81681-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler |
Mutation-based Compliance Testing for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pp. 55-60, 2021, ACM, 978-1-4503-7999-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Dun-An Yang, Jing-Jia Liou, Harry H. Chen |
Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 30th IEEE Asian Test Symposium, ATS 2021, Matsuyama, Ehime, Japan, November 22-25, 2021, pp. 133-138, 2021, IEEE, 978-1-6654-4051-6. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy |
Extended RISC-V hardware architecture for future digital communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
5GWF ![In: 4th IEEE 5G World Forum, 5GWF 2021, Montreal, QC, Canada, October 13-15, 2021, pp. 224-229, 2021, IEEE, 978-1-6654-4308-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt |
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-8, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-8, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, pp. 391-397, 2021, IEEE, 978-1-6654-3759-2. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Sarah L. Harris, Daniel Chaver, Luis Piñuel, José Ignacio Gómez Pérez, M. Hamza Liaqat, Zubair L. Kakakhel, Olof Kindgren, Robert Owen |
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, pp. 145-150, 2021, IEEE, 978-1-6654-3759-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Demonstrating custom SIMD instruction development for a RISC-V softcore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, pp. 139, 2021, IEEE, 978-1-6654-3759-2. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Xiaofeng Zou, Tuo Li, Rengang Li, Linlin Yang, Xiankun Wang, Changhong Wang |
Porting and FPGA Implementation of LXDE Desktop Environment Based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSAE ![In: CSAE 2021: The 5th International Conference on Computer Science and Application Engineering, Sanya, China, October 19 - 21, 2021, pp. 76:1-76:5, 2021, ACM, 978-1-4503-8985-3. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Rami Elkhatib, Reza Azarderakhsh, Mehran Mozaffari Kermani |
Accelerated RISC-V for SIKE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 28th IEEE Symposium on Computer Arithmetic, ARITH 2021, Lyngby, Denmark, June 14-16, 2021, pp. 131-138, 2021, IEEE, 978-1-6654-2293-2. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 28th IEEE Symposium on Computer Arithmetic, ARITH 2021, Lyngby, Denmark, June 14-16, 2021, pp. 53, 2021, IEEE, 978-1-6654-2293-2. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Jeferson González-Gómez, Steven Ávila-Ardón, Jonathan Rojas-González, Andres Stephen-Cantillano, Jorge Castro-Godínez, Carlos Salazar-García, Muhammad Shafique 0001, Jörg Henkel |
TailoredCore: Generating Application-Specific RISC-V-based Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-7670-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ludovico Poli, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier |
Design and Implementation of a RISC V Processor on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSN ![In: 17th International Conference on Mobility, Sensing and Networking, MSN 2021, Exeter, United Kingdom, December 13-15, 2021, pp. 161-166, 2021, IEEE, 978-1-6654-0668-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Tao Lu |
Exploring Storage Device Characteristics of A RISC-V Little-core SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: IEEE International Conference on Networking, Architecture and Storage, NAS 2021, Riverside, CA, USA, October 24-26, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-7744-1. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota |
Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIT ![In: ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20 - 22, 2021, pp. 13-18, 2021, ACM, 978-1-4503-8493-3. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Gage Hills |
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: ISPD '21: International Symposium on Physical Design, Virtual Event, USA, March 22-24, 2021, pp. 73, 2021, ACM, 978-1-4503-8300-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xi Wang 0009, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel A. Kinsy, Yong Chen 0001 |
xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 35th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2021, Portland, OR, USA, May 17-21, 2021, pp. 454-463, 2021, IEEE, 978-1-6654-4066-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Najdet Charaf, Ahmed Kamaleldin, Martin Thümmler, Diana Göhringer |
RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2021, Portland, OR, USA, June 17-21, 2021, pp. 172-179, 2021, IEEE, 978-1-6654-3577-2. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Rod Burns, Colin Davidson, Aidan Dodds |
Enabling OpenCL and SYCL for RISC-V processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWOCL ![In: IWOCL'21: International Workshop on OpenCL, Munich Germany, April, 2021, pp. 15:1, 2021, ACM, 978-1-4503-9033-0. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt 0001, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic |
A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 47th ESSCIRC 2021 - European Solid State Circuits Conference, ESSCIR 2021, Grenoble, France, September 13-22, 2021, pp. 259-262, 2021, IEEE, 978-1-6654-3751-6. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Stephen A. Zekany, Jielun Tan, James A. Connelly, Ronald G. Dreslinski |
RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education, Virtual Event, USA, March 13-20, 2021, pp. 1096-1102, 2021, ACM, 978-1-4503-8062-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Elena Suvorova |
RISC V Based Reconfigurable Manager for Event Transmission in SpaceFibre Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FRUCT ![In: 29th Conference of Open Innovations Association, FRUCT 2021, Tampere, Finland, May 12-14, 2021, pp. 356-365, 2021, IEEE, 978-952-69244-5-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Meng Liu |
The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: CODES/ISSS 2021, International Conference on Hardware/Software Codesign and System Synthesis, Virtual Event, October 10-13, 2021, pp. 23-24, 2021, ACM, 978-1-4503-9076-7. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini |
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021, pp. 1-9, 2021, IEEE, 978-1-6654-4507-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Chen Bai, Qi Sun 0002, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong |
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021, pp. 1-9, 2021, IEEE, 978-1-6654-4507-8. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Islam Elsadek, Eslam Yahya Tawfik |
RISC-V Resource-Constrained Cores: A Survey and Energy Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 19th IEEE International New Circuits and Systems Conference, NEWCAS 2021, Toulon, France, June 13-16, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-2429-5. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 24th Forum on specification & Design Languages, FDL 2021, Antibes, France, September 8-10, 2021, pp. 1-7, 2021, IEEE, 978-1-6654-1825-6. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Flavia Caforio, Pierpaolo Iannicelli, Michele Paolino, Daniel Raho |
VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 10th Mediterranean Conference on Embedded Computing, MECO 2021, Budva, Montenegro, June 7-10, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3912-1. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Alban Gruin, Thomas Carle, Hugues Cassé, Christine Rochange |
Speculative Execution and Timing Predictability in an Open Source RISC-V Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: 42nd IEEE Real-Time Systems Symposium, RTSS 2021, Dortmund, Germany, December 7-10, 2021, pp. 393-404, 2021, IEEE, 978-1-6654-2802-6. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Mehmet Alp Sarkisla, Arda Yurdakul |
SIMDify: Framework for SIMD-Processing with RISC-V Scalar Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSW ![In: ACSW '21: 2021 Australasian Computer Science Week Multiconference, Dunedin, New Zealand, 1-5 February, 2021, pp. 7:1-7:10, 2021, ACM, 978-1-4503-8956-3. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Jyun-Kai Lai, Wuu Yang |
Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: ICPP Workshops 2021: 50th International Conference on Parallel Processing, Virtual Event / Lemont (near Chicago), IL, USA, August 9-12, 2021, pp. 13:1-13:9, 2021, ACM, 978-1-4503-8441-4. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Che-Chia Lin, Chao-Lin Lee, Jenq-Kuen Lee, Howard Wang, Ming-Yu Hung |
Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: ICPP Workshops 2021: 50th International Conference on Parallel Processing, Virtual Event / Lemont (near Chicago), IL, USA, August 9-12, 2021, pp. 15:1-15:8, 2021, ACM, 978-1-4503-8441-4. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | YuJin Kwak, YoungBeom Kim, Seog Chung Seo |
Parallel Implementation of PIPO Block Cipher on 32-bit RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications - 22nd International Conference, WISA 2021, Jeju Island, South Korea, August 11-13, 2021, Revised Selected Papers, pp. 183-193, 2021, Springer, 978-3-030-89431-3. The full citation details ...](Pics/full.jpeg) |
2021 |
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