Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne |
Metric Definition for Circuit Speed Optimization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida |
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Grzegorz Tosik, Frédéric Gaffiot, Zbigniew Lisik, Ian O'Connor, Faress Tissafi-Drissi |
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim |
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel |
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jérôme Lescot, François J. R. Clément |
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Acquaviva, Tajana Simunic, Vinay Deolalikar, Sumit Roy 0002 |
Remote Power Control of Wireless Network Interfaces. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Maurizio Bruno, Alberto Macii, Massimo Poncino |
A Statistic Power Model for Non-synthetic RTL Operators. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida |
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Eugeni Isern 0001, Miquel Roca 0001, Francesc Moll |
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Acquaviva, Alessandro Bogliolo |
A Bottom-Up Approach to On-Chip Signal Integrity. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Juan-Chico, Enrico Macii (eds.) |
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria |
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins |
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Wen-Tsong Shiue, Weetit Wanalertlak |
Advanced Cell Modeling Techniques Based on Polynomial Expressions. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Cuomo |
Architectural Challenges for the Next Decade Integrated Platforms. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Chee Lee, Wen-Tsong Shiue |
Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne |
CMOS Gate Sizing under Delay Constraint. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Louis Scheffer |
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Vineela Manne, Akhilesh Tyagi |
An Adiabatic Charge Pump Based Charge Recycling Design Style. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Anatoly Prihozhy, Marco Mattavelli, Daniel Mlynek |
Data Dependences Critical Path Evaluation at C/C++ System Level Description. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel |
Interconnect Driven Low Power High-Level Synthesis. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Dongsheng Wang 0012, Peter Suaris, Nan-Chi Chou |
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin |
Statistic Implementation of QDI Asynchronous Primitives. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Frank Gilbert, Norbert Wehn |
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Tae-Chan Kim 0003, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim |
Low Power Response Time Accelerator with Full Resolution for LCD Panel. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni |
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Byung-Soo Choi, Dong-Ik Lee |
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jean Oudinot |
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner |
Switching Activity Estimation in Non-linear Architectures. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Pradeep Varma, Ashutosh Chakraborty |
Low-Voltage, Double-Edge-Triggered Flip Flop. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis 0001, Stilianos Siskos, Adonios Thanailakis |
FPGA Architecture Design and Toolset for Logic Implementation. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán 0001 |
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | G. Privitera, Francesco Pessolano |
Analysis of High-Speed Logic Families. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | José Luis Rosselló, Jaume Segura 0001 |
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Ramesh Karri, Piyush Mishra |
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney |
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin |
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Akihito Sakanaka, Toshinori Sato |
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Emil Hjalmarson, Robert Hägglund, Lars Wanhammar |
Design Space Exploration and Trade-Offs in Analog Amplifier Design. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Tae-Chan Kim 0003, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim |
Low Power Cache with Successive Tag Comparison Algorithm. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Blotti, Maurizio Castellucci, Roberto Saletti |
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne |
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | José Luis Rosselló, Jaume Segura 0001 |
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Vojin G. Oklobdzija |
Clocking and Clocked Storage Elements in Multi-GHz Environment. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Torsten Mahnke, Walter Stechele, Wolfgang Hoeld |
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin 0001 |
Power Consumption Estimation of a C Program for Data-Intensive Applications. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero |
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Luca Benini, Alberto Macii, Enrico Macii |
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Gaetano Palumbo |
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Christian Piguet |
The First Quartz Electronic Watch. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Saas, Josef A. Nossek |
Resonant Multistage Charging of Dominant Capacitances. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Hoang Q. Dao, Vojin G. Oklobdzija |
Performance Comparison of VLSI Adders Using Logical Effort. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose |
Energy-Efficient Design of the Reorder Buffer. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Periklis Neofotistos, K. Kosmatopoulos, Theodore Laopoulos, Labros Bisdounis |
Instrumentation Set-up for Instruction Level Power Modeling. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers |
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis |
Power Efficient Vector Quantization Design Using Pixel Truncation. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco |
Synthetic Generation of Events for Address-Event-Representation Communications. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo |
Low-Power FSMs in FPGA: Encoding Alternatives. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
One-Hot, State Encod-ing, FPGA, Low-Power, Finite State Machine |
1 | Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal |
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga |
Register File Energy Reduction by Operand Data Reuse. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Spiridon Nikolaidis 0001, Haroula Pournara, Alexander Chatzigeorgiou |
Output Waveform Evaluation of Basic Pass Transistor Structure. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni |
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Daniel González, Antonio García 0001, Graham A. Jullien, Javier Ramírez 0001, Luis Parrilla 0001, Antonio Lloris-Ruíz |
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Xuemei Zhao, Yizheng Ye |
Design and Realization of a Low Power Register File Using Energy Model. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Armin Windschiegl, Paul Zuber, Walter Stechele |
Exploiting Metal Layer Characteristics for Low-Power Routing. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001 |
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
An Approach to Energy Consumption Modeling in RC Ladder Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta 0001 |
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Claudia Kretzschmar, Robert Siegmund, Dietmar Müller 0001 |
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Philippe Maurine, Nadine Azémard, Daniel Auvergne |
Structure Independent Representation of Output Transition Time for CMOS Library. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David T. Blaauw |
Robust SAT-Based Search Algorithm for Leakage Power Reduction. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Kiyoo Itoh 0001 |
Trends in Ultralow-Voltage RAM Technology. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel |
An Improved Power Macro-Model for Arithmetic Datapath Components. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard |
Low-Power Asynchronous A/D Conversion. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán 0001, David Guerrero Martos |
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Kyu-won Choi, Abhijit Chatterjee |
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Achim Freimann |
Probabilistic Power Estimation for Digital Signal Processing Architectures. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Bertrand Hochet, Antonio J. Acosta 0001, Manuel J. Bellido (eds.) |
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos |
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Igor Lemberski, Mark B. Josephs |
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Juan Antonio Carballo, Sani R. Nassif |
Impact of Technology in Power-Grid-Induced Noise. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Artur Wróblewski, Florian Auernhammer, Josef A. Nossek |
Minimizing Spurious Switching Activities in CMOS Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Rosario Mita, Gaetano Palumbo |
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Pessolano, Joep L. W. Kessels, Ad M. G. Peeters |
MDSP: A High-Performance Low-Power DSP Architecture. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Fabrice Picot, Philippe Coll, Daniel Auvergne |
Crosstalk Measurement Technique for CMOS ICs. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Oscar Garnica, Juan Lanchares, Román Hermida |
A New Methodology to Design Low-Power Asynchronous Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin |
Dynamic Voltage Scheduling for Real Time Asynchronous Systems. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Toshinori Sato, Itsujiro Arita |
Reducing Energy Consumption via Low-Cost Value Prediction. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Gregorio Cappuccino, Giuseppe Cocorullo |
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos D. Zervas, G. Pagkless, Minas Dasygenis, Dimitrios Soudris |
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Claude Arm, Jean-Marc Masgonty, Christian Piguet |
Double-Latch Clocking Scheme for Low-Power I.P. Cores. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Rene van Leuken 0001, Reinder Nouta, Alexander de Graaf |
Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis |
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Alexis De Vos, Bart Desoete, Artur Adamski, Piotr Pietrzak, Maciej Sibínski, Tomasz Widerski |
Design of Reversible Logic Circuits by Means of Control Gates. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Kristof Denolf, Peter Vos, Jan Bormans, Ivo Bolsens |
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Saas, Andreas Schlaffer, Josef A. Nossek |
An Adiabatic Multiplier. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Holger Sedlak |
Low Power Design Techniques for Contactless Chipcards. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis |
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|