Search results for "PLL"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Martin Kreißig, Steffen Wittrock, Florian Protze, Romain Lebrun, Karla J. Merazzo, Marie Claire Cyrille, Ricardo Ferreira 0003, Paolo Bortolotti, Ursula Ebels, Vincent Cros, Frank Ellinger	Hybrid PLL system for spin torque oscillators utilizing custom ICs in 0.18 μm BiCMOS.	MWSCAS	2017	DBLP DOI BibTeX RDF
13	B. Dinesh Kumar 0001, Sumit Pandey, Puneet Arora, Rahul Shrestha	A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector.	ISED	2017	DBLP DOI BibTeX RDF
13	Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
13	Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu	Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.	ASP-DAC	2017	DBLP DOI BibTeX RDF
13	Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata	An FPGA-compatible PLL-based sensor against fault injection attack.	ASP-DAC	2017	DBLP DOI BibTeX RDF
13	Peng Tao 0005, Fengxiang Wang, Xuezhu Mei, Jinxin Lin	PLL with Piecewise Judgement Function for SMO Beased Sensorless Control of PMSM.	ES	2017	DBLP DOI BibTeX RDF
13	Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Peter G. M. Baltus	Noise analysis of a BJT-based charge pump for low-noise PLL applications.	ECCTD	2017	DBLP DOI BibTeX RDF
13	G. Sionek, L. H. A. Lolis, J. P. C. Cunha, M. L. Matias, André Augusto Mariano, Bernardo Leite	Double quadrature bandpass sampling for a PLL and mixer-less low-IF multistandard receiver.	LASCAS	2017	DBLP DOI BibTeX RDF
13	Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura	Spur reduction by self-injection loop in a fractional-N PLL.	ICECS	2017	DBLP DOI BibTeX RDF
13	Henning Schütz, Albrecht Rothermel, Stefan Gambach	Clock Recovery Gated PLL for Periodically Interrupted and 100% ASK Modulated Signals for a Medical Implant.	NGCAS	2017	DBLP DOI BibTeX RDF
13	Minuk Heo, Sunghyun Bae, Jayeol Lee, Cheonsu Kim, Minjae Lee	Quantizer-less proportional path fractional-N digital PLL with a low-power high-gain time amplifier and background multi-point spur calibration.	ESSCIRC	2017	DBLP DOI BibTeX RDF
13	Ivan Milosavljevic, Ðorde Przulj, Dusan Krcum, Darko M. Tasovac, Lazar Saranovac, Vladimir M. Milovanovic	An FMCW fractional-N PLL-based synthesizer for integrated 79 GHz automotive radar sensors.	EUROCON	2017	DBLP DOI BibTeX RDF
13	Rui Zhao 0014, Daniel T. Gladwin, David A. Stone	A hybrid wireless PLL for phase shift control based maximum efficiency point tracking in resonant wireless power transmission systems.	IECON	2017	DBLP DOI BibTeX RDF
13	Hongguang Zhang, Pan Xue, Zhiliang Hong	A 4.6-5.6 GHz constant KVCO low phase noise LC-VCO and an optimized automatic frequency calibrator applied in PLL frequency synthesizer.	IECON	2017	DBLP DOI BibTeX RDF
13	Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Gilles Jacquemod	Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology.	NEWCAS	2017	DBLP DOI BibTeX RDF
13	Dongyi Liao, Fa Foster Dai, Bram Nauta, Eric A. M. Klumperink	Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking.	CICC	2017	DBLP DOI BibTeX RDF
13	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2017	DBLP DOI BibTeX RDF
13	Ruixin Wang, Fa Foster Dai	A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression.	CICC	2017	DBLP DOI BibTeX RDF
13	Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001	A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS.	CICC	2017	DBLP DOI BibTeX RDF
13	Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon	A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.	CICC	2017	DBLP DOI BibTeX RDF
13	Jeffrey Chuang, Harish Krishnaswamy	19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOM.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw	8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Yuming He, Yao-Hong Liu, Takashi Kuramochi, Johan H. C. van den Heuvel, Benjamin Busze, Nereo Markulic, Christian Bachmann, Kathleen Philips	24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa	8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho	24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh	19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio	21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Yudong Zhang 0006, Xiaofeng Liu, Woogeun Rhee, Hanjun Jiang, Zhihua Wang 0001	A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Arthur H. M. van Roermund	Modeling and analysis of the effects of PLL phase noise on FMCW radar performance.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Kehan Zhu, Sakkarapani Balagopal, Xinyu Wu 0002, Vishal Saxena	Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina	Semianalytical model for high speed analysis of all-digital PLL clock-generating networks.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Tuan Minh Vo, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Aaron Bluestone, Ryan Kaveh, Luke Theogarajan	An analog phase prediction based fractional-N PLL.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer	Optimization of the PLL based TRNG design using the genetic algorithm.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Federico Bizzarri, Angelo Brambilla, Alessandro Colombo, Sergio Callegari	Constant-time discontinuity map for forward sensitivity analysis to initial conditions: Spurs detection in fractional-N PLL as a case study.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Marco Crepaldi, Gian Nicola Angotzi, Antonio Maviglia, Luca Berdondini	A 1 Gpps asynchronous logic OOK IR-UWB transmitter based on master-slave PLL synthesis.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Srinivas Gude, Chia-Chi Chu	Three-phase grid synchronization PLL using multiple delayed signal cancellation under adverse grid voltage conditions.	IAS	2017	DBLP DOI BibTeX RDF
13	Sangsu Lee, Jaehun Jun, Chulwoo Kim	A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations.	ISOCC	2017	DBLP DOI BibTeX RDF
13	Yongho Lee, Seungsoo Kim, Hyunchol Shin	Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS.	ISOCC	2017	DBLP DOI BibTeX RDF
13	Sanjeev Jain, Nan Zhang, Leonid Belostotski	Millimeter-wave CMOS PLL using a push-push oscillator.	CCECE	2017	DBLP DOI BibTeX RDF
13	Yi Xiong, Koyo Asaishi, Natsuko Milli, Yifei Sun 0001, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi 0001	Constant on-time controlled four-phase buck converter via two ways of saw-tooth-wave circuit and PLL circuit.	ISPACS	2017	DBLP DOI BibTeX RDF
13	Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo 0003	A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes.	NCCET	2017	DBLP DOI BibTeX RDF
13	Chun-Yu Lin 0002, Tun-Ju Wang, Tsung-Hsien Lin	A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
13	Jens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns	A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
13	Chun-Yu Lin 0002, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin	An ultra-low power 169-nA 32.768-kHz fractional-N PLL.	A-SSCC	2017	DBLP DOI BibTeX RDF
13	Shunli Ma, Jili Sheng, Ning Li 0007, Junyan Ren	A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
13	Bin Zheng, Lianjun Deng, Mamoru Sawahashi, Norifumi Kamiya	Performance of pilot symbol assisted and PLL phase noise estimation and compensation for high-order circular QAM.	APCC	2017	DBLP DOI BibTeX RDF
13	Mohieddine Benammar, Antonio S. P. Gonzales	Position Measurement Using Sinusoidal Encoders and All-Analog PLL Converter With Improved Dynamic Performance.	IEEE Trans. Ind. Electron.	2016	DBLP DOI BibTeX RDF
13	George C. Konstantopoulos, Qing-Chang Zhong, Wen-Long Ming	PLL-Less Nonlinear Current-Limiting Controller for Single-Phase Grid-Tied Inverters: Design, Stability Analysis, and Operation Under Grid Faults.	IEEE Trans. Ind. Electron.	2016	DBLP DOI BibTeX RDF
13	Kunhee Cho, Ranjit Gharpurey	A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu	A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng 0001, Kenichi Okada, Akira Matsuzawa	A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Cheng-Ru Ho, Mike Shuo-Wei Chen	A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa	A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng 0001, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa	A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng 0001, Kenichi Okada, Akira Matsuzawa	A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Wei Zhang, Youde Hu, Li-Rong Zheng 0001	Design and simulation of a standing wave oscillator based PLL.	Frontiers Inf. Technol. Electron. Eng.	2016	DBLP DOI BibTeX RDF
13	Yunlu Li, Dazhi Wang, Wei Han, Sen Tan, Xifeng Guo	Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter.	IEEE Access	2016	DBLP DOI BibTeX RDF
13	Mohieddine Benammar, Antonio S. P. Gonzales	A Novel PLL Resolver Angle Position Indicator.	IEEE Trans. Instrum. Meas.	2016	DBLP DOI BibTeX RDF
13	Dongsheng Yang 0002, Tomohiro Ueno, Wei Deng 0001, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu 0001, Kenichi Okada, Akira Matsuzawa	A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
13	Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada	An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
13	Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou	A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
13	Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang	An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
13	Zeyang Liu, Masaru Takeuchi, Masahiro Nakajima, Toshio Fukuda, Yasuhisa Hasegawa, Qiang Huang 0002	Batch Fabrication of Microscale Gear-Like Tissue by Alginate-Poly-L-lysine (PLL) Microcapsules System.	IEEE Robotics Autom. Lett.	2016	DBLP DOI BibTeX RDF
13	Mahdi Ashabani, Francisco D. Freijedo, Saeed Golestan, Josep M. Guerrero	Inducverters: PLL-Less Converters With Auto-Synchronization and Emulated Inertia Capability.	IEEE Trans. Smart Grid	2016	DBLP DOI BibTeX RDF
13	Andrea Tilli, Christian Conficoni	Semiglobal Uniform Asymptotic Stability of an Easy-to-Implement PLL-Like Sensorless Observer for Induction Motors.	IEEE Trans. Autom. Control.	2016	DBLP DOI BibTeX RDF
13	J. A. Guinea	Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
13	Manas Kumar Hati, Tarun Kanti Bhattacharyya	A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
13	Abhijit Kulkarni, Vinod John	Design of a High-Performance High-Pass Generalized Integrator Based Single-Phase PLL.	CoRR	2016	DBLP BibTeX RDF
13	Li Cong, Xin Li, Tian Jin, Song Yue, Rui Xue	An Adaptive INS-Aided PLL Tracking Method for GNSS Receivers in Harsh Environments.	Sensors	2016	DBLP DOI BibTeX RDF
13	Ehsan Ali, Christian Hangmann, Christian Hedayat, Fayrouz Haddad, Wenceslas Rahajandraibe, Ulrich Hilleringmann	Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
13	Chih-Lu Wei, Shen-Iuan Liu	A Digital PLL Using Oversampling Delta-Sigma TDC.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
13	Dongil Lee, Taeho Lee 0001, Young-Ju Kim 0001, Lee-Sup Kim	A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
13	Sung-Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min-Hyeong Kim, Woo-Young Choi	A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
13	Archit Joshi, Gagan Midha	Bandwidth Compensation Technique for Digital PLL.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
13	Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath	Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
13	Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu	A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
13	Guanjun Jing, Qiping Yuan, Yinping Miao, Zhihong Chen, Xiaoping Yang	A novel PLL based on reference current for three-phase power systems.	DSP	2016	DBLP DOI BibTeX RDF
13	Monika Bhardwaj, Sujata Pandey	Design of a wide output range and reduced current mismatch charge pump PLL with improved performance.	ICACCI	2016	DBLP DOI BibTeX RDF
13	Markus Scholl, Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen	A high efficiency straightforward design and verification methodology for PLL systems.	MWSCAS	2016	DBLP DOI BibTeX RDF
13	Hany A. Hamed, Ahmed F. Abdou, E. E. El-Kholy, Ehab H. E. Bayoumi	Adaptive cascaded delayed signal cancelation PLL based fuzzy controller under grid disturbances.	MWSCAS	2016	DBLP DOI BibTeX RDF
13	Klaus Schmalz, Johannes Borngräber, Selahattin Berk Yilmaz, Nick Rothbart, Dietmar Kissinger, Heinz-Wilhelm Hübers	Gas spectroscopy with 245 GHz circuits in SiGe BiCMOS and Frac-N PLL for frequency ramps.	IEEE SENSORS	2016	DBLP DOI BibTeX RDF
13	Juzheng Han, Xiaoping Liao	Design, measurement and evaluation for PLL application of a wideband MEMS phase detector.	IEEE SENSORS	2016	DBLP DOI BibTeX RDF
13	Dongsheng Yang 0002, Wei Deng 0001, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.	ASP-DAC	2016	DBLP DOI BibTeX RDF
13	Jun-Di Sun, Guang-Zhong Cao, Su-Dan Huang, Hong Qiu	Software-based resolver-to-digital converter using the PLL tracking algorithm.	URAI	2016	DBLP DOI BibTeX RDF
13	Magdalena Fuentes, Pablo Zinemanas, Pablo Cancela, José Antonio Apolinário	Detection of ENF discontinuities using PLL for audio authenticity.	LASCAS	2016	DBLP DOI BibTeX RDF
13	Eugene Koskin	Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks.	ICECS	2016	DBLP DOI BibTeX RDF
13	Zied Koubaa, Mohamed Ali 0001, René Landry Jr., Mohamad Sawan	Amplitude demodulation based on synchronized sampling by a PLL circuit.	ICECS	2016	DBLP DOI BibTeX RDF
13	Aidan Marnane, Valerio Marotta, Michael Peter Kennedy	Yet another spur mechanism in a charge-pump based Fractional-N PLL.	ICECS	2016	DBLP DOI BibTeX RDF
13	Zakia Berber, Samir Kameche	Design and simulation of PLL frequency synthesizer for LTE mobile communications.	ICMCS	2016	DBLP DOI BibTeX RDF
13	Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx	A Fractional-n subsampling PLL based on a digital-to-time converter.	MIPRO	2016	DBLP DOI BibTeX RDF
13	Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Wei-Zen Chen, Po-I Kuo	A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa	A 2 GHz 3.1 mW type-I digital ring-based PLL.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Abhirup Lahiri, Nitin Gupta	A 0.0175mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Werner Grollitsch, Roberto Nonis	A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Ying Wu 0003, Mina Shahmohammadi, Yue Chen, Ping Lu 0002, Robert Bogdan Staszewski	A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise.	ESSCIRC	2016	DBLP DOI BibTeX RDF
13	Elena Trancho, Edorta Ibarra, Antoni Arias, Cristobal Salazar, Iraide Lopez, Alavro Diaz de Guereñu, Alberto Peña	A novel PMSM hybrid sensorless control strategy for EV applications based on PLL and HFI.	IECON	2016	DBLP DOI BibTeX RDF