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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 153 occurrences of 86 keywords
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Results
Found 1868 publication records. Showing 1868 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Martin Kreißig, Steffen Wittrock, Florian Protze, Romain Lebrun, Karla J. Merazzo, Marie Claire Cyrille, Ricardo Ferreira 0003, Paolo Bortolotti, Ursula Ebels, Vincent Cros, Frank Ellinger |
Hybrid PLL system for spin torque oscillators utilizing custom ICs in 0.18 μm BiCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 910-913, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | B. Dinesh Kumar 0001, Sumit Pandey, Puneet Arora, Rahul Shrestha |
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 7th International Symposium on Embedded Computing and System Design, ISED 2017, Durgapur, India, December 18-20, 2017, pp. 1-5, 2017, IEEE, 978-1-5386-3032-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 13-14, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu |
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 43-44, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata |
An FPGA-compatible PLL-based sensor against fault injection attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 39-40, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Peng Tao 0005, Fengxiang Wang, Xuezhu Mei, Jinxin Lin |
PLL with Piecewise Judgement Function for SMO Beased Sensorless Control of PMSM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ES ![In: 5th International Conference on Enterprise Systems, ES 2017, Beijing, China, September 22-24, 2017, pp. 190-194, 2017, IEEE, 978-1-5386-0936-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Peter G. M. Baltus |
Noise analysis of a BJT-based charge pump for low-noise PLL applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Catania, Italy, September 4-6, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-3974-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | G. Sionek, L. H. A. Lolis, J. P. C. Cunha, M. L. Matias, André Augusto Mariano, Bernardo Leite |
Double quadrature bandpass sampling for a PLL and mixer-less low-IF multistandard receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 8th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2017, Bariloche, Argentina, February 20-23, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5859-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura |
Spur reduction by self-injection loop in a fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pp. 260-263, 2017, IEEE, 978-1-5386-1911-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Henning Schütz, Albrecht Rothermel, Stefan Gambach |
Clock Recovery Gated PLL for Periodically Interrupted and 100% ASK Modulated Signals for a Medical Implant. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NGCAS ![In: New Generation of CAS, NGCAS 2017, Genova, Italy, September 6-9, 2017, pp. 97-100, 2017, IEEE, 978-1-5090-6447-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Minuk Heo, Sunghyun Bae, Jayeol Lee, Cheonsu Kim, Minjae Lee |
Quantizer-less proportional path fractional-N digital PLL with a low-power high-gain time amplifier and background multi-point spur calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017, pp. 147-150, 2017, IEEE, 978-1-5090-5025-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Ivan Milosavljevic, Ðorde Przulj, Dusan Krcum, Darko M. Tasovac, Lazar Saranovac, Vladimir M. Milovanovic |
An FMCW fractional-N PLL-based synthesizer for integrated 79 GHz automotive radar sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: IEEE EUROCON 2017 -17th International Conference on Smart Technologies, Ohrid, Macedonia, July 6-8, 2017, pp. 265-270, 2017, IEEE, 978-1-5090-3843-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Rui Zhao 0014, Daniel T. Gladwin, David A. Stone |
A hybrid wireless PLL for phase shift control based maximum efficiency point tracking in resonant wireless power transmission systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29 - November 1, 2017, pp. 5301-5306, 2017, IEEE, 978-1-5386-1127-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Hongguang Zhang, Pan Xue, Zhiliang Hong |
A 4.6-5.6 GHz constant KVCO low phase noise LC-VCO and an optimized automatic frequency calibrator applied in PLL frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29 - November 1, 2017, pp. 8337-8342, 2017, IEEE, 978-1-5386-1127-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Gilles Jacquemod |
Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017, pp. 121-124, 2017, IEEE, 978-1-5090-4991-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Dongyi Liao, Fa Foster Dai, Bram Nauta, Eric A. M. Klumperink |
Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Shravan S. Nagam, Peter R. Kinget |
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Ruixin Wang, Fa Foster Dai |
A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001 |
A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon |
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Jeffrey Chuang, Harish Krishnaswamy |
19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 328-329, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw |
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 148-149, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Yuming He, Yao-Hong Liu, Takashi Kuramochi, Johan H. C. van den Heuvel, Benjamin Busze, Nereo Markulic, Christian Bachmann, Kathleen Philips |
24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 420-421, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim |
8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 154-155, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa |
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 150-151, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho |
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 422-423, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh |
19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 326-327, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio |
21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 358-359, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yudong Zhang 0006, Xiaofeng Liu, Woogeun Rhee, Hanjun Jiang, Zhihua Wang 0001 |
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Arthur H. M. van Roermund |
Modeling and analysis of the effects of PLL phase noise on FMCW radar performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Kehan Zhu, Sakkarapani Balagopal, Xinyu Wu 0002, Vishal Saxena |
Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina |
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Tuan Minh Vo, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Aaron Bluestone, Ryan Kaveh, Luke Theogarajan |
An analog phase prediction based fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer |
Optimization of the PLL based TRNG design using the genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Federico Bizzarri, Angelo Brambilla, Alessandro Colombo, Sergio Callegari |
Constant-time discontinuity map for forward sensitivity analysis to initial conditions: Spurs detection in fractional-N PLL as a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Marco Crepaldi, Gian Nicola Angotzi, Antonio Maviglia, Luca Berdondini |
A 1 Gpps asynchronous logic OOK IR-UWB transmitter based on master-slave PLL synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Srinivas Gude, Chia-Chi Chu |
Three-phase grid synchronization PLL using multiple delayed signal cancellation under adverse grid voltage conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: 2017 IEEE Industry Applications Society Annual Meeting, Cincinnati, OH, USA, October 1-5, 2017, pp. 1-8, 2017, IEEE, 978-1-5090-4894-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Sangsu Lee, Jaehun Jun, Chulwoo Kim |
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017, pp. 180-181, 2017, IEEE, 978-1-5386-2285-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yongho Lee, Seungsoo Kim, Hyunchol Shin |
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017, pp. 230-231, 2017, IEEE, 978-1-5386-2285-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Sanjeev Jain, Nan Zhang, Leonid Belostotski |
Millimeter-wave CMOS PLL using a push-push oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 30th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2017, Windsor, ON, Canada, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5538-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yi Xiong, Koyo Asaishi, Natsuko Milli, Yifei Sun 0001, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi 0001 |
Constant on-time controlled four-phase buck converter via two ways of saw-tooth-wave circuit and PLL circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: 2017 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2017, Xiamen, China, November 6-9, 2017, pp. 741-746, 2017, IEEE, 978-1-5386-2159-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo 0003 |
A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCCET ![In: Computer Engineering and Technology - 21st CCF Conference, NCCET 2017, Xiamen, China, August 16-18, 2017, Revised Selected Papers, pp. 45-51, 2017, Springer, 978-981-10-7843-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Chun-Yu Lin 0002, Tun-Ju Wang, Tsung-Hsien Lin |
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 253-256, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Jens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns |
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 325-328, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Chun-Yu Lin 0002, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin |
An ultra-low power 169-nA 32.768-kHz fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 45-48, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Shunli Ma, Jili Sheng, Ning Li 0007, Junyan Ren |
A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 321-324, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Bin Zheng, Lianjun Deng, Mamoru Sawahashi, Norifumi Kamiya |
Performance of pilot symbol assisted and PLL phase noise estimation and compensation for high-order circular QAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCC ![In: 23rd Asia-Pacific Conference on Communications, APCC 2017, Perth, Australia, December 11-13, 2017, pp. 1-6, 2017, IEEE, 978-1-7405-2390-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Mohieddine Benammar, Antonio S. P. Gonzales |
Position Measurement Using Sinusoidal Encoders and All-Analog PLL Converter With Improved Dynamic Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 63(4), pp. 2414-2423, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | George C. Konstantopoulos, Qing-Chang Zhong, Wen-Long Ming |
PLL-Less Nonlinear Current-Limiting Controller for Single-Phase Grid-Tied Inverters: Design, Stability Analysis, and Operation Under Grid Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 63(9), pp. 5582-5591, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Kunhee Cho, Ranjit Gharpurey |
A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(11), pp. 2639-2650, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu |
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(8), pp. 1771-1784, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng 0001, Kenichi Okada, Akira Matsuzawa |
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(5), pp. 1246-1260, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Cheng-Ru Ho, Mike Shuo-Wei Chen |
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(12), pp. 3216-3230, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(10), pp. 2345-2356, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng 0001, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(6), pp. 1385-1397, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng 0001, Kenichi Okada, Akira Matsuzawa |
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(7), pp. 1630-1640, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx |
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(12), pp. 3078-3092, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Wei Zhang, Youde Hu, Li-Rong Zheng 0001 |
Design and simulation of a standing wave oscillator based PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 17(3), pp. 258-264, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Yunlu Li, Dazhi Wang, Wei Han, Sen Tan, Xifeng Guo |
Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 4, pp. 6272-6282, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Mohieddine Benammar, Antonio S. P. Gonzales |
A Novel PLL Resolver Angle Position Indicator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 65(1), pp. 123-131, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Dongsheng Yang 0002, Tomohiro Ueno, Wei Deng 0001, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu 0001, Kenichi Okada, Akira Matsuzawa |
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(6), pp. 632-640, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada |
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(2), pp. 275-284, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou |
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(4), pp. 481-490, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang |
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(4), pp. 440-443, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Zeyang Liu, Masaru Takeuchi, Masahiro Nakajima, Toshio Fukuda, Yasuhisa Hasegawa, Qiang Huang 0002 |
Batch Fabrication of Microscale Gear-Like Tissue by Alginate-Poly-L-lysine (PLL) Microcapsules System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Robotics Autom. Lett. ![In: IEEE Robotics Autom. Lett. 1(1), pp. 206-212, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Mahdi Ashabani, Francisco D. Freijedo, Saeed Golestan, Josep M. Guerrero |
Inducverters: PLL-Less Converters With Auto-Synchronization and Emulated Inertia Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Smart Grid ![In: IEEE Trans. Smart Grid 7(3), pp. 1660-1674, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Andrea Tilli, Christian Conficoni |
Semiglobal Uniform Asymptotic Stability of an Easy-to-Implement PLL-Like Sensorless Observer for Induction Motors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Autom. Control. ![In: IEEE Trans. Autom. Control. 61(11), pp. 3612-3618, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | J. A. Guinea |
Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(10), pp. 1828-1839, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 52, pp. 134-146, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Abhijit Kulkarni, Vinod John |
Design of a High-Performance High-Pass Generalized Integrator Based Single-Phase PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.04114, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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13 | Li Cong, Xin Li, Tian Jin, Song Yue, Rui Xue |
An Adaptive INS-Aided PLL Tracking Method for GNSS Receivers in Harsh Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 16(2), pp. 146, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Ehsan Ali, Christian Hangmann, Christian Hedayat, Fayrouz Haddad, Wenceslas Rahajandraibe, Ulrich Hilleringmann |
Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(3), pp. 347-358, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Chih-Lu Wei, Shen-Iuan Liu |
A Digital PLL Using Oversampling Delta-Sigma TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(7), pp. 633-637, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Dongil Lee, Taeho Lee 0001, Young-Ju Kim 0001, Lee-Sup Kim |
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 733-737, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Sung-Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min-Hyeong Kim, Woo-Young Choi |
A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(6), pp. 548-552, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Archit Joshi, Gagan Midha |
Bandwidth Compensation Technique for Digital PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(11), pp. 1044-1048, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath |
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(10), pp. 20160328, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu |
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(2), pp. 20150950, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Guanjun Jing, Qiping Yuan, Yinping Miao, Zhihong Chen, Xiaoping Yang |
A novel PLL based on reference current for three-phase power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 2016 IEEE International Conference on Digital Signal Processing, DSP 2016, Beijing, China, October 16-18, 2016, pp. 164-167, 2016, IEEE, 978-1-5090-4165-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Monika Bhardwaj, Sujata Pandey |
Design of a wide output range and reduced current mismatch charge pump PLL with improved performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2016 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2016, Jaipur, India, September 21-24, 2016, pp. 2644-2649, 2016, IEEE, 978-1-5090-2029-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Markus Scholl, Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen |
A high efficiency straightforward design and verification methodology for PLL systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Hany A. Hamed, Ahmed F. Abdou, E. E. El-Kholy, Ehab H. E. Bayoumi |
Adaptive cascaded delayed signal cancelation PLL based fuzzy controller under grid disturbances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Klaus Schmalz, Johannes Borngräber, Selahattin Berk Yilmaz, Nick Rothbart, Dietmar Kissinger, Heinz-Wilhelm Hübers |
Gas spectroscopy with 245 GHz circuits in SiGe BiCMOS and Frac-N PLL for frequency ramps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE SENSORS ![In: 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, pp. 1-3, 2016, IEEE, 978-1-4799-8287-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Juzheng Han, Xiaoping Liao |
Design, measurement and evaluation for PLL application of a wideband MEMS phase detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE SENSORS ![In: 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, pp. 1-3, 2016, IEEE, 978-1-4799-8287-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Dongsheng Yang 0002, Wei Deng 0001, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016, pp. 1-2, 2016, IEEE, 978-1-4673-9569-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Jun-Di Sun, Guang-Zhong Cao, Su-Dan Huang, Hong Qiu |
Software-based resolver-to-digital converter using the PLL tracking algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
URAI ![In: 13th International Conference on Ubiquitous Robots and Ambient Intelligence, URAI 2016, Xian, China, August 19-22, 2016, pp. 719-723, 2016, IEEE, 978-1-5090-0821-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Magdalena Fuentes, Pablo Zinemanas, Pablo Cancela, José Antonio Apolinário |
Detection of ENF discontinuities using PLL for audio authenticity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 7th Latin American Symposium on Circuits & Systems, LASCAS 2016, Florianopolis, Brazil, February 28 - March 2, 2016, pp. 79-82, 2016, IEEE, 978-1-4673-7835-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Eugene Koskin |
Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 434-435, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Zied Koubaa, Mohamed Ali 0001, René Landry Jr., Mohamad Sawan |
Amplitude demodulation based on synchronized sampling by a PLL circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 684-687, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Aidan Marnane, Valerio Marotta, Michael Peter Kennedy |
Yet another spur mechanism in a charge-pump based Fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 452-455, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Zakia Berber, Samir Kameche |
Design and simulation of PLL frequency synthesizer for LTE mobile communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCS ![In: 5th International Conference on Multimedia Computing and Systems, ICMCS 2016, Marrakech, Morocco, September 29 - October 1, 2016, pp. 745-748, 2016, IEEE, 978-1-5090-5146-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx |
A Fractional-n subsampling PLL based on a digital-to-time converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: 39th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2016, Opatija, Croatia, May 30 - June 3, 2016, pp. 66-71, 2016, IEEE, 978-953-233-086-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 197-200, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Wei-Zen Chen, Po-I Kuo |
A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 347-350, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
A 2 GHz 3.1 mW type-I digital ring-based PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 205-208, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Abhirup Lahiri, Nitin Gupta |
A 0.0175mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 339-342, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Werner Grollitsch, Roberto Nonis |
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 201-204, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Ying Wu 0003, Mina Shahmohammadi, Yue Chen, Ping Lu 0002, Robert Bogdan Staszewski |
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 209-212, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
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13 | Elena Trancho, Edorta Ibarra, Antoni Arias, Cristobal Salazar, Iraide Lopez, Alavro Diaz de Guereñu, Alberto Peña |
A novel PMSM hybrid sensorless control strategy for EV applications based on PLL and HFI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, October 23-26, 2016, pp. 6669-6674, 2016, IEEE, 978-1-5090-3474-1. The full citation details ...](Pics/full.jpeg) |
2016 |
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