Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han 0003, Xiaoyang Zeng, Xu Cheng 0002	A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Weizhen Wang, Jun Han 0003, Xu Cheng 0002, Xiaoyang Zeng	An energy-efficient crypto-extension design for RISC-V.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Imad Al Assir, Mohamad El Iskandarani, Hadi Rayan Al Sandid, Mazen A. R. Saghir	Arrow: A RISC-V Vector Accelerator for Machine Learning Inference.	CoRR	2021	DBLP BibTeX RDF
13	Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim	Supporting CUDA for an extended RISC-V GPU architecture.	CoRR	2021	DBLP BibTeX RDF
13	Asmit De, Swaroop Ghosh	HeapSafe: Securing Unprotected Heaps in RISC-V.	CoRR	2021	DBLP BibTeX RDF
13	Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Andrew Wright, Adam Chlipala	A Multipurpose Formal RISC-V Specification.	CoRR	2021	DBLP BibTeX RDF
13	Flavia Caforio, Pierpaolo Iannicelli, Michele Paolino, Daniel Raho	VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms.	CoRR	2021	DBLP BibTeX RDF
13	Tao Lu	A Survey on RISC-V Security: Hardware and Architecture.	CoRR	2021	DBLP BibTeX RDF
13	Bruno Sá, José Martins, Sandro Pinto 0001	A First Look at RISC-V Virtualization from an Embedded Systems Perspective.	CoRR	2021	DBLP BibTeX RDF
13	Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee	Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.	CoRR	2021	DBLP BibTeX RDF
13	Carlton Shepherd, Konstantinos Markantonakis, Georges-Axel Jaloyan	LIRA-V: Lightweight Remote Attestation for Constrained RISC-V Devices.	CoRR	2021	DBLP BibTeX RDF
13	Stefan Steinegger, David Schrammel, Samuel Weiser, Pascal Nasahl, Stefan Mangard	SERVAS! Secure Enclaves via RISC-V Authenticryption Shield.	CoRR	2021	DBLP BibTeX RDF
13	David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto 0001	PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability.	CoRR	2021	DBLP BibTeX RDF
13	Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework.	CoRR	2021	DBLP BibTeX RDF
13	Avani Dave, Nilanjan Banerjee, Chintan Patel	CARE: Lightweight Attack Resilient Secure Boot Architecturewith Onboard Recovery for RISC-V based SOC.	CoRR	2021	DBLP BibTeX RDF
13	Joao Mario Domingos, Pedro Tomás, Leonel Sousa	Supporting RISC-V Performance Counters through Performance analysis tools for Linux (Perf).	CoRR	2021	DBLP BibTeX RDF
13	Georges-Axel Jaloyan, Konstantinos Markantonakis, Raja Naeem Akram, David Robin, Keith Mayes, David Naccache	Return-Oriented Programming on RISC-V.	CoRR	2021	DBLP BibTeX RDF
13	Odysseas Chatzopoulos, George-Marios Fragkoulis, George Papadimitriou 0001, Dimitris Gizopoulos	Towards Accurate Performance Modeling of RISC-V Designs.	CoRR	2021	DBLP BibTeX RDF
13	Cristóbal Ramírez Lazo, César-Alejandro Hernández-Calderón, Oscar Palomar, Osman Sabri Unsal, Marco Antonio Ramírez, Adrián Cristal	A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.	CoRR	2021	DBLP BibTeX RDF
13	Blaise Tine, Fares Elsabbagh, Krishna Praveen Yalamarthy, Hyesoon Kim	Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch.	CoRR	2021	DBLP BibTeX RDF
13	Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk	Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions.	CoRR	2021	DBLP BibTeX RDF
13	Mahya Morid Ahmadi, Faiq Khalid, Muhammad Shafique 0001	Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities.	CoRR	2021	DBLP BibTeX RDF
13	Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone	On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors.	J. Aerosp. Inf. Syst.	2021	DBLP DOI BibTeX RDF
13	Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf	The design of scalar AES Instruction Set Extensions for RISC-V.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2021	DBLP DOI BibTeX RDF
13	Alexandre Adomnicai, Thomas Peyrin	Fixslicing AES-like Ciphers New bitsliced AES speed records on ARM-Cortex M and RISC-V.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2021	DBLP DOI BibTeX RDF
13	Jipeng Zhang, Junhao Huang, Zhe Liu 0001, Sujoy Sinha Roy	Time-memory Trade-offs for Saber+ on Memory-constrained RISC-V.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Ben Marshall, Daniel Page, Thinh Hung Pham	A lightweight ISE for ChaCha on RISC-V.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Hwajeong Seo, Hyeokdong Kwon, Siwoo Eum, Kyungbae Jang, Hyunjun Kim, Hyunji Kim, Minjoo Sim, Gyeongju Song, Wai-Kong Lee	All the Polynomial Multiplication You Need on RISC-V.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Rami Elkhatib, Reza Azarderakhsh, Mehran Mozaffari Kermani	Accelerated RISC-V for Post-Quantum SIKE.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Huimin Li 0004, Nele Mentens, Stjepan Picek	A Scalable SIMD RISC-V based Processor with Customized Vector Extensions for CRYSTALS-Kyber.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Haifeng Zhang 0010, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang, Shengbing Zhang	A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System.	Sensors	2021	DBLP DOI BibTeX RDF
13	Shiwei Yuan, Lei Li, Ji Yang, Yuanhang He, Wanting Zhou, Jin Li	Real-time detection of hardware trojan attacks on General-Purpose Registers in a RISC-V processor.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
13	Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Xuan-Tu Tran, Cong-Kha Pham	A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
13	Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler	Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.	J. Syst. Archit.	2021	DBLP DOI BibTeX RDF
13	Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Cong-Kha Pham	A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.	HCS	2021	DBLP DOI BibTeX RDF
13	Todd M. Austin, Austin Harris 0001, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari	Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware.	HCS	2021	DBLP DOI BibTeX RDF
13	David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau	Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.	HCS	2021	DBLP DOI BibTeX RDF
13	Christoph Spang 0001, Florian Meisel, Andreas Koch 0001	RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement.	SAMOS	2021	DBLP DOI BibTeX RDF
13	Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini	RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.	SAMOS	2021	DBLP DOI BibTeX RDF
13	Yi-Wen Hung, Yao-Tse Chang, Shuenn-Yuh Lee, Chou-Ching K. Lin, Gia-Shing Shieh	An Energy-efficient and Programmable RISC-V CNN Coprocessor for Real-time Epilepsy Detection and Identification on Wearable Devices.	ICCE-TW	2021	DBLP DOI BibTeX RDF
13	Fearghal Morgan, Arthur Beretta, Ian Gallivan, Joseph Clancy, Frédéric Rousseau 0001, Roshan George, László Bakó, Frank Callaly	RISC-V Online Tutor.	REV	2021	DBLP DOI BibTeX RDF
13	Sarah Hesham, Mohamed Shalan, M. Watheq El-Kharashi, Mohamed Dessouky	Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison.	MWSCAS	2021	DBLP DOI BibTeX RDF
13	Michael Platzer, Peter P. Puschner	Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation.	ECRTS	2021	DBLP DOI BibTeX RDF
13	Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad Ahmed, Hala Ibrahim, Hassan Mostafa	Implementation and Functional Verification of RISC-V Core for Secure IoT Applications.	ICM	2021	DBLP DOI BibTeX RDF
13	Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler	Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
13	Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, Ahmad-Reza Sadeghi	In Hardware We Trust? From TPM to Enclave Computing on RISC-V.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
13	Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi	AFTAB: A RISC-V Implementation with Configurable Gateways for Security.	EWDTS	2021	DBLP DOI BibTeX RDF
13	Abdelrahman Sobeih Hussein, Hassan Mostafa	ASIC-FPGA Gap for a RISC-V Core Implementation for DNN Applications.	NILES	2021	DBLP DOI BibTeX RDF
13	Boria Pérez, Alexander Fell, John D. Davis	Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC.	DATE	2021	DBLP DOI BibTeX RDF
13	Marouene Boubakri, Fausto Chiatante, Belhassen Zouari	Towards a firmware TPM on RISC-V.	DATE	2021	DBLP DOI BibTeX RDF
13	Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser	Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core.	DATE	2021	DBLP DOI BibTeX RDF
13	Robert Balas, Luca Benini	RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis.	DATE	2021	DBLP DOI BibTeX RDF
13	Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi	SealPK: Sealable Protection Keys for RISC-V.	DATE	2021	DBLP DOI BibTeX RDF
13	Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger	RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension.	DSD	2021	DBLP DOI BibTeX RDF
13	Muhammad Ali 0010, Matthias von Ameln, Diana Goehringer	Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing.	DSD	2021	DBLP DOI BibTeX RDF
13	Gianluca Bellocchi, Alessandro Capotondi, Francesco Conti 0001, Andrea Marongiu	A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment.	DSD	2021	DBLP DOI BibTeX RDF
13	Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems.	DSD	2021	DBLP DOI BibTeX RDF
13	Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules.	DSD	2021	DBLP DOI BibTeX RDF
13	Vasileios Tsoutsouras, Orestis Kaparounakis, Bilgesu Arif Bilgin, Chatura Samarakoon, James Timothy Meech, Jan Heck, Phillip Stanley-Marbell	The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor.	MICRO	2021	DBLP DOI BibTeX RDF
13	Haonan Li 0009, Weijie Huang, Mingde Ren, Hongyi Lu, Zhenyu Ning, Heming Cui, Fengwei Zhang	A Novel Memory Management for RISC-V Enclaves.	HASP@MICRO	2021	DBLP DOI BibTeX RDF
13	Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim	Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics.	MICRO	2021	DBLP DOI BibTeX RDF
13	Evelina Forno, Andrea Spitale, Enrico Macii, Gianvito Urgese	Configuring an Embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge Computing Applications.	MCSoC	2021	DBLP DOI BibTeX RDF
13	Risikesh RK, Sharad Sinha, Nanditha P. Rao	Variable Bit-Precision Vector Extension for RISC-V Based Processors.	MCSoC	2021	DBLP DOI BibTeX RDF
13	Takuto Kanamori, Kenji Kise	RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions.	MCSoC	2021	DBLP DOI BibTeX RDF
13	Md. Ashraful Islam, Kenji Kise	Efficient Resource Shared RISC-V Multicore Processor.	MCSoC	2021	DBLP DOI BibTeX RDF
13	Jaume Abella 0001, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker 0001, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández 0001, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer 0002, Stefan Wagner 0001, Francesco Regazzoni 0001	Security, Reliability and Test Aspects of the RISC-V Ecosystem.	ETS	2021	DBLP DOI BibTeX RDF
13	Ramon Wirsch, Christian Hochberger	Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.	ARCS	2021	DBLP DOI BibTeX RDF
13	Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler	Mutation-based Compliance Testing for RISC-V.	ASP-DAC	2021	DBLP DOI BibTeX RDF
13	Dun-An Yang, Jing-Jia Liou, Harry H. Chen	Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study.	ATS	2021	DBLP DOI BibTeX RDF
13	Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy	Extended RISC-V hardware architecture for future digital communication systems.	5GWF	2021	DBLP DOI BibTeX RDF
13	Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt	Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.	MBMV	2021	DBLP BibTeX RDF
13	Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler	Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion.	MBMV	2021	DBLP BibTeX RDF
13	Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk	Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions.	FPL	2021	DBLP DOI BibTeX RDF
13	Sarah L. Harris, Daniel Chaver, Luis Piñuel, José Ignacio Gómez Pérez, M. Hamza Liaqat, Zubair L. Kakakhel, Olof Kindgren, Robert Owen	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education.	FPL	2021	DBLP DOI BibTeX RDF
13	Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk	Demonstrating custom SIMD instruction development for a RISC-V softcore.	FPL	2021	DBLP DOI BibTeX RDF
13	Xiaofeng Zou, Tuo Li, Rengang Li, Linlin Yang, Xiankun Wang, Changhong Wang	Porting and FPGA Implementation of LXDE Desktop Environment Based on RISC-V.	CSAE	2021	DBLP DOI BibTeX RDF
13	Rami Elkhatib, Reza Azarderakhsh, Mehran Mozaffari Kermani	Accelerated RISC-V for SIKE.	ARITH	2021	DBLP DOI BibTeX RDF
13	Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes.	ARITH	2021	DBLP DOI BibTeX RDF
13	Jeferson González-Gómez, Steven Ávila-Ardón, Jonathan Rojas-González, Andres Stephen-Cantillano, Jorge Castro-Godínez, Carlos Salazar-García, Muhammad Shafique 0001, Jörg Henkel	TailoredCore: Generating Application-Specific RISC-V-based Cores.	LASCAS	2021	DBLP DOI BibTeX RDF
13	Ludovico Poli, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier	Design and Implementation of a RISC V Processor on FPGA.	MSN	2021	DBLP DOI BibTeX RDF
13	Tao Lu	Exploring Storage Device Characteristics of A RISC-V Little-core SoC.	NAS	2021	DBLP DOI BibTeX RDF
13	Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota	Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System.	ACIT	2021	DBLP DOI BibTeX RDF
13	Gage Hills	Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor.	ISPD	2021	DBLP DOI BibTeX RDF
13	Xi Wang 0009, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel A. Kinsy, Yong Chen 0001	xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing.	IPDPS	2021	DBLP DOI BibTeX RDF
13	Najdet Charaf, Ahmed Kamaleldin, Martin Thümmler, Diana Göhringer	RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip.	IPDPS Workshops	2021	DBLP DOI BibTeX RDF
13	Rod Burns, Colin Davidson, Aidan Dodds	Enabling OpenCL and SYCL for RISC-V processors.	IWOCL	2021	DBLP DOI BibTeX RDF
13	Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt 0001, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic	A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.	ESSCIRC	2021	DBLP DOI BibTeX RDF
13	Stephen A. Zekany, Jielun Tan, James A. Connelly, Ronald G. Dreslinski	RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA.	SIGCSE	2021	DBLP DOI BibTeX RDF
13	Elena Suvorova	RISC V Based Reconfigurable Manager for Event Transmission in SpaceFibre Networks.	FRUCT	2021	DBLP DOI BibTeX RDF
13	Meng Liu	The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress.	CODES+ISSS	2021	DBLP DOI BibTeX RDF
13	Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini	Banshee: A Fast LLVM-Based RISC-V Binary Translator.	ICCAD	2021	DBLP DOI BibTeX RDF
13	Chen Bai, Qi Sun 0002, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong	BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.	ICCAD	2021	DBLP DOI BibTeX RDF
13	Islam Elsadek, Eslam Yahya Tawfik	RISC-V Resource-Constrained Cores: A Survey and Energy Comparison.	NEWCAS	2021	DBLP DOI BibTeX RDF
13	Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler	RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems.	FDL	2021	DBLP DOI BibTeX RDF
13	Flavia Caforio, Pierpaolo Iannicelli, Michele Paolino, Daniel Raho	VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms.	MECO	2021	DBLP DOI BibTeX RDF
13	Alban Gruin, Thomas Carle, Hugues Cassé, Christine Rochange	Speculative Execution and Timing Predictability in an Open Source RISC-V Core.	RTSS	2021	DBLP DOI BibTeX RDF
13	Mehmet Alp Sarkisla, Arda Yurdakul	SIMDify: Framework for SIMD-Processing with RISC-V Scalar Instruction Set.	ACSW	2021	DBLP DOI BibTeX RDF
13	Jyun-Kai Lai, Wuu Yang	Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms.	ICPP Workshops	2021	DBLP DOI BibTeX RDF
13	Che-Chia Lin, Chao-Lin Lee, Jenq-Kuen Lee, Howard Wang, Ming-Yu Hung	Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions.	ICPP Workshops	2021	DBLP DOI BibTeX RDF
13	YuJin Kwak, YoungBeom Kim, Seog Chung Seo	Parallel Implementation of PIPO Block Cipher on 32-bit RISC-V Processor.	WISA	2021	DBLP DOI BibTeX RDF