Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Yngvar Berg	Static ultra-low-voltage high-speed CMOS logic and latches.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero	Fast fixed-point optimization of DSP algorithms.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Roberto Cardu, Eleonora Franchi, Roberto Guerrieri, Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo	Characterization of chip-to-chip wireless interconnections based on capacitive coupling.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Ding-Guo Lin, Bing-Hsun Lu, Herming Chiueh	An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Alessandro Panella, Marco D. Santambrogio, Francesco Redaelli, Fabio Cancare, Donatella Sciuto	A design workflow for dynamically reconfigurable multi-FPGA systems.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet	A high-speed high-resolution low-phase noise oscillator using self-timed rings.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Khawla Hamwi, Omar Hammami	Design and implementation of MPSoC single chip with butterfly network.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici	Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Roberto Gioiosa	Towards sustainable exascale computing.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Ji Kong, Peilin Liu	A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Bruno Zatt, Cláudio Machado Diniz, Luciano Volcan Agostini, Sergio Bampi	Timing and interface communication analysis of H.264/AVC encoder using SystemC model.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Pramod Kumar Meher	An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Chengmo Yang, Alex Orailoglu	Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Bruno Francisco, Frederico Pratas, Leonel Sousa	Unifying stream based and reconfigurable computing to design application accelerators.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Maher Jridi, Ayman Alfalou	A low-power, high-speed DCT architecture for image compression: Principle and implementation.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Debora Matos, Miklecio Costa, Luigi Carro, Altamiro Amadeu Susin	Network interface to synchronize multiple packets on NoC-based Systems-on-Chip.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	João S. Altermann, Eduardo A. C. da Costa, Sergio Bampi	Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni	Adaptive logical control of RF LNA performances for efficient energy consumption.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Chengmo Yang, Chun Jason Xue, Alex Orailoglu	Fine-grained adaptive CMP cache sharing through access history exploitation.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Sergey Sofer, Valery Neiman, Eyal Melamed-Cohen	Synchronous duty cycle correction circuit.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Jayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar	Towards reverse engineering the brain: Modeling abstractions and simulation frameworks.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Christos Ttofis, Agathoklis Papadopoulos, Theocharis Theocharides, Maria K. Michael, Demosthenes Doumenis	A reconfigurable MPSoC-based QAM modulation architecture.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin	A decimal squarer with efficient partial product generation.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert	Spatial EM jamming: A countermeasure against EM Analysis?	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Tom De Weyer, Frank Van Reeth, Eddy Flerackers	Smart camera SoC system for interactive real-time real-brush based digital painting systems.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Ronaldo Husemann, Mariano Majolo, Victor Guimarães 0002, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima	Hardware integrated quantization solution for improvement of computational H.264 encoder module.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Mariza Botelho, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Érika F. Cota, Luigi Carro	A broad strategy to detect crosstalk faults in network-on-chip interconnects.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii	Power-aware partitioning of data converters.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani	Logic synthesis and testability of D-reducible functions.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Roman Plyaskin, Alejandro Masrur, Martin Geier 0001, Samarjit Chakraborty, Andreas Herkersdorf	High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Rawan Abdel-Khalek, Valeria Bertacco	SoCGuard: A runtime verification solution for the functional correctness of SoCs.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Christian Benkeser, Andreas Bubenhofer, Qiuting Huang	A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Markus Wenk, Lukas Bruderer, Andreas Burg, Christoph Studer	Area- and throughput-optimized VLSI architecture of sphere decoding.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan	Enhancing post-silicon processor debug with Incremental Cache state Dumping.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Hui Shao, Chi-Ying Tsui, Wing-Hung Ki	A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Gabriel Caffarena, Carlos Carreras	Architectural synthesis of DSP circuits under simultaneous error and time constraints.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Yngvar Berg	Ultra low voltage and high speed CMOS flip-flop using floating-gates.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Kuo-Che Hong, Herming Chiueh	A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1		18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010	VLSI-SoC	2010	DBLP BibTeX RDF
1	Wen-Chung Tsai, Kuo-Chih Chu, Sao-Jie Chen, Yu Hen Hu	TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on Chip.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Mohamed Abdelsalam, M. Wahba, M. Abdelmoneum, David Duarte, Yehia Ismail	Supporting circuitry for a fully integrated micro electro mechanical (MEMS) oscillator in 45 nm CMOS technology.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Paolo Meloni, Simone Secchi, Luigi Raffo	Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do	A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Andy Motten, Luc Claesen	A binary adaptable window SoC architecture for a stereo vision based depth field processor.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Nicolas Ventroux, Tanguy Sassolas, Raphaël David, Guillaume Blanc, Alexandre Guerre, Charly Bechara	SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Trends and techniques for energy efficient architectures.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Jing Guo, Bing Liu 0012, George Jie Yuan	A highly linear wide dynamic range detector for cell recording with microelectrode arrays.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo	An improved RNS generator 2n +/- k based on threshold logic.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Oscar Alonso, Lluis Freixas, Joan Canals, Ekawahyu Susilo, Ángel Dieguez	Control electronics integration toward endoscopic capsule robot performing legged locomotion and illumination.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	Power-aware FPGA routing fabrics and design tools.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Wei-Che Tseng, Chun Jason Xue, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha	Optimal scheduling to minimize non-volatile memory access time with hardware cache.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Christos Baloukas, Lazaros Papadopoulos, Robert Pyka, Dimitrios Soudris, Peter Marwedel	An automatic framework for dynamic data structures optimization in C.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Zohreh Karimi, Majid Sarrafzadeh	Fine-grained post placement voltage assignment considering level shifter overhead.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Tsung-Yi Ho, Sheng-Hung Liu	Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Alzemiro Henrique Lucas da Silva, Alexandre M. Amory, Fernando Gehm Moraes	Crosstalk Fault Tolerant NoC: Design and Evaluation.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Ian O'Connor, Junchen Liu, Kotb Jabeur, Nataliya Yakymets, Renaud Daviot, David Navarro, Pierre-Emmanuel Gaillardon, Fabien Clermidy, Maimouna Amadou, Gabriela Nicolescu	Emerging Technologies and Nanoscale Computing Fabrics.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	António Gusmão, Luís Miguel Silveira, José Monteiro 0001	Power Macro-Modeling Using an Iterative LS-SVM Method.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Dieison Antonello Deprá, Sergio Bampi	Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert	Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Yann Oddos, Katell Morin-Allory, Dominique Borrione	From Assertion-Based Verification to Assertion-Based Synthesis.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing	Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Gustavo Girão, Daniel Barcelos, Flávio Rech Wagner	Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Sergio Bampi, Ricardo Reis 0001	Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Petru Bogdan Bacinschi, Manfred Glesner	A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler	SWORD: A SAT like prover using word level information.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Eduardo Wenzel Brião, Daniel Barcelos, Fabio Wronski, Flávio Rech Wagner	Impact of task migration in NoC-based MPSoCs for soft real-time applications.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	C. M. Markan, Priti Gupta	Neuromorphic building blocks for adaptable cortical feature maps.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Sujan Pandey, Christian Genz, Rolf Drechsler	Co-synthesis of custom on-chip bus and memory for MPSoC architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Nan Jiang 0009, David Money Harris	Parallelized radix-2 scalable Montgomery multiplier.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Luigi Carro	Transparent acceleration of data dependent instructions for general purpose processors.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Sergio Johann Filho, Fabiano Hessel	A VHDL based approach for fast and accurate energy consumption estimations.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Youssef Serrestou, Vincent Beroulle, Chantal Robach	Impact of hardware emulation on the verification quality improvement.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jean Carlo Hamerski, Everton Reckziegel, Fernanda Lima Kastensmidt	Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Almitra Pradhan, Ranga Vemuri	Regression based circuit matrix models for accurate performance estimation of analog circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Satnam Singh	New parallel programming techniques for hardware design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris	A software-supported methodology for designing high-performance 3D FPGA architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay	A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	Incremental placement for structured ASICs using the transportation problem.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jürgen Becker 0001, Adam Donlin, Michael Hübner 0001	New tool support and architectures in adaptive reconfigurable computing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Brian Cody, Justin Madigan, Spencer MacDonald, Kenneth W. Hsu	High speed SOC design for blowfish cryptographic algorithm.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo A. Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler	A Flexible Design Flow for a Low Power RFID Tag.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Pranav Vaidya, Jaehwan John Lee	Simulation of hybrid computer architectures: simulators, methodologies and recommendations.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Alin Razafindraibe, Michel Robert, Philippe Maurine	Improvement of dual rail logic as a countermeasure against DPA.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Rishi Bhooshan, Bindu P. Rao	Optimum IR drop models for estimation of metal resource requirements for power distribution network.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris	Implementing cellular automata modeled applications on network-on-chip platforms.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Chih-Wen Lu, Yen-Chih Shen, Meng-Lieh Sheu	A high-driving class-AB buffer amplifier with a new pseudo source follower.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jaemoon Kim, Sangkwon Na, Chong-Min Kyung	A low-power deblocking filter architecture for H.264 advanced video coding.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Aline Mello 0001, Ney Laert Vilar Calazans	Rate-based scheduling policy for QoS flows in networks on chip.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vagner S. Rosa, Altamiro Amadeu Susin, Sergio Bampi	An HDTV H.264 deblocking filter in FPGA with RGB video output.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Osnat Keren, Ilya Levin, Radomir S. Stankovic	Use of gray decoding for implementation of symmetric functions.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio	ReCPU: A parallel and pipelined architecture for regular expression matching.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Parth Malani, Prakash Mukre, Qinru Qiu	Power optimization for conditional task graphs in DVS enabled multiprocessor systems.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto	An adaptive genetic algorithm for dynamically reconfigurable modules allocation.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro	Qualification of behavioral level design validation for AMS & RF SoCs.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Test data compression and TAM design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	J. Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce, Magdy A. Bayoumi	Hybrid multiplierless FIR filter architecture based on NEDA.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Low power on-chip thermal sensors based on wires.	VLSI-SoC	2007	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )