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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 543 occurrences of 346 keywords
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Results
Found 836 publication records. Showing 836 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Alexander Iliev, Sean W. Smith |
Prototyping an Armored Data Vault: Rights Management on Big Brother's Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Privacy Enhancing Technologies ![In: Privacy Enhancing Technologies, Second International Workshop, PET 2002, San Francisco, CA, USA, April 14-15, 2002, Revised Papers, pp. 144-159, 2002, Springer, 3-540-00565-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Dmitri Asonov, Johann Christoph Freytag |
Almost Optimal Private Information Retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Privacy Enhancing Technologies ![In: Privacy Enhancing Technologies, Second International Workshop, PET 2002, San Francisco, CA, USA, April 14-15, 2002, Revised Papers, pp. 209-223, 2002, Springer, 3-540-00565-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Efficient realization of privacy services |
11 | Christian Aumüller, Peter Bier, Wieland Fischer, Peter Hofreiter, Jean-Pierre Seifert |
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 260-275, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Spike attacks, Software countermeasures, Transient fault model, RSA, Chinese Remainder Theorem, Fault attacks, Hardware security, Bellcore attack |
11 | Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis |
A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(2-3), pp. 223-240, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Christian Hochberger, Rolf Hoffmann, Klaus-Peter Völkmann, Stefan Waldschmidt |
The Cellular Processor Architecture CEPRA-1X and Its Configuration by CDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 898-905, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | L. Levinson, Reinhard Männer, M. Sessler, Harald Simmler |
Preemptive Multitasking on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 301-302, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Gerald G. Pechanek, Stamatis Vassiliadis |
The ManArray( Embedded Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1348-1355, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco |
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 17-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fault Injection, Software Fault-Tolerance |
11 | B. Bosi, Guy Bois, Yvon Savaria |
Reconfigurable pipelined 2-D convolvers for fast digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(3), pp. 299-308, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Lode Nachtergaele, Ivo Bolsens |
A Scalable Architecture for MPEG-4 Wavelet Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 23(1), pp. 93-107, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack |
Instruction Set Extensions for MPEG-4 Video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 23(1), pp. 27-49, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari |
Development System for FPGA-Based Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 266-267, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Ronald Laufer, R. Reed Taylor, Herman Schmit |
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 200-208, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Romain Kamdem, Alain Fonkoua, Andre Zenatti |
Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 640-645, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
code-sign, scheduling, real time, Codesign, hardware/software partitioning, target architecture |
11 | Mario Salerno, F. Sargeni, V. Bonaiuto, Sergio Taraglio, Andrea Zanela |
A dedicated hardware system for CNN stereo vision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 501-504, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Klaus Herrmann 0002, Jan Otterstedt, Hartwig Jeschke, M. Kuboschek |
A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm2 monolithic implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 284-291, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Alberto Broggi, Gianni Conte, Francesco Gregoretti, Claudio Sansoè, Roberto Passerone, Leonardo Maria Reyneri |
Design and Implementation of the PAPRICA Parallel Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(1), pp. 5-18, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Samvel K. Shoukourian |
A Unified Design Methodology for Offline and Online Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(2), pp. 73-79, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Gunter Haug, Wolfgang Rosenstiel |
Reconfigurable Hardware as Shared Resource in Multipurpose Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 149-158, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Timothy J. Callahan, John Wawrzynek |
Instruction-Level Parallelism for Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 248-257, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Gunter Haug, Wolfgang Rosenstiel |
Reconfigurable Hardware as Shared Resource for Parallel Threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 320-321, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Philip Heng Wai Leong, P. K. Tsang, T. K. Lee |
A FPGA Based Forth Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 254-255, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Alex R. Bugeja, W. Yang |
A reconfigurable VLSI coprocessing system for the block matching algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(3), pp. 329-337, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Ram Kesavan, Dhabaleswar K. Panda 0001 |
Optimal Multicast with Packetization and Network Interface Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 370-377, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Network Interface Support and Packetization, Multicast, Interconnection Network, Broadcast, Wormhole Routing, Collective communication, Networks of Workstations, Link Contention |
11 | Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard |
Programmable active memories: reconfigurable systems come of age. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 56-69, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Bonifacio Martín-del-Brío, Javier Blasco-Alberto |
Hardware-Oriented Models for VLSI Implementation of Self-Organizing Maps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: From Natural to Artificial Neural Computation, International Workshop on Artificial Neural Networks, IWANN '95, Malaga-Torremolinos, Spain, June 7-9, 1995, Proceedings, pp. 712-719, 1995, Springer, 3-540-59497-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
11 | Stephen D. Scott 0001, Ashok Samal, Sharad C. Seth |
HGA: A Hardware-Based Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 53-59, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms |
11 | Peter Soderquist, Miriam Leeser |
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 132-139, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Newton-Raphson method, Goldschmidt's algorithm, microprocessor, Floating-point, division, square root, SRT |
11 | H. A. Chow, Hussein M. Alnuweiri, Steve Casselman |
FPGA-based transformable computers for fast digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 197-203, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
11 | Ulrich Holtmann, Rolf Ernst |
Experiments with low-level speculative computation based on multiple branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(3), pp. 262-267, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
11 | Myung Hoon Sunwoo, J. K. Aggarwal |
A Sliding Memory Plane Array Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(6), pp. 601-612, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures |
11 | Klaus Gaedke, Hartwig Jeschke, Peter Pirsch |
A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(2-3), pp. 159-169, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
11 | Rajesh K. Gupta 0001, Giovanni De Micheli |
Hardware-Software Cosynthesis for Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(3), pp. 29-41, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
11 | Kam-Fai Wong, M. Howard Williams |
CLARE - A Prolog Database Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGSMALL/PC Symposium ![In: Proceedings of the 1990 ACM SIGSMALL/PC Symposium on Small Systems, March 28-30, 1990. Crystal City, VA, USA, pp. 172-177, 1990, ACM, 0-89791-347-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Prolog |
11 | Fadi N. Sibai, Karan L. Watson, Mi Lu |
Design and performance measurements of a parallel machine for the unification algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 21-30, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
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11 | Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson |
RISCs versus CISCs for Prolog: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 136-145, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
Prolog, RISC, CISC |
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