Search results for "coprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Alexander Iliev, Sean W. Smith	Prototyping an Armored Data Vault: Rights Management on Big Brother's Computer.	Privacy Enhancing Technologies	2002	DBLP DOI BibTeX RDF
11	Dmitri Asonov, Johann Christoph Freytag	Almost Optimal Private Information Retrieval.	Privacy Enhancing Technologies	2002	DBLP DOI BibTeX RDF	Efficient realization of privacy services
11	Christian Aumüller, Peter Bier, Wieland Fischer, Peter Hofreiter, Jean-Pierre Seifert	Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures.	CHES	2002	DBLP DOI BibTeX RDF	Spike attacks, Software countermeasures, Transient fault model, RSA, Chinese Remainder Theorem, Fault attacks, Hardware security, Bellcore attack
11	Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis	A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
11	Christian Hochberger, Rolf Hoffmann, Klaus-Peter Völkmann, Stefan Waldschmidt	The Cellular Processor Architecture CEPRA-1X and Its Configuration by CDL.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
11	L. Levinson, Reinhard Männer, M. Sessler, Harald Simmler	Preemptive Multitasking on FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
11	Gerald G. Pechanek, Stamatis Vassiliadis	The ManArray( Embedded Processor Architecture.	EUROMICRO	2000	DBLP DOI BibTeX RDF
11	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco	Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.	IOLTW	2000	DBLP DOI BibTeX RDF	Fault Injection, Software Fault-Tolerance
11	B. Bosi, Guy Bois, Yvon Savaria	Reconfigurable pipelined 2-D convolvers for fast digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Lode Nachtergaele, Ivo Bolsens	A Scalable Architecture for MPEG-4 Wavelet Quantization.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
11	Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack	Instruction Set Extensions for MPEG-4 Video.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
11	Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari	Development System for FPGA-Based Digital Circuits.	FCCM	1999	DBLP DOI BibTeX RDF
11	Ronald Laufer, R. Reed Taylor, Herman Schmit	PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing.	FCCM	1999	DBLP DOI BibTeX RDF
11	Romain Kamdem, Alain Fonkoua, Andre Zenatti	Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory.	ICCD	1999	DBLP DOI BibTeX RDF	code-sign, scheduling, real time, Codesign, hardware/software partitioning, target architecture
11	Mario Salerno, F. Sargeni, V. Bonaiuto, Sergio Taraglio, Andrea Zanela	A dedicated hardware system for CNN stereo vision.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
11	Klaus Herrmann 0002, Jan Otterstedt, Hartwig Jeschke, M. Kuboschek	A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm2 monolithic implementation.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Alberto Broggi, Gianni Conte, Francesco Gregoretti, Claudio Sansoè, Roberto Passerone, Leonardo Maria Reyneri	Design and Implementation of the PAPRICA Parallel Architecture.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
11	Samvel K. Shoukourian	A Unified Design Methodology for Offline and Online Testing.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
11	Gunter Haug, Wolfgang Rosenstiel	Reconfigurable Hardware as Shared Resource in Multipurpose Computers.	FPL	1998	DBLP DOI BibTeX RDF
11	Timothy J. Callahan, John Wawrzynek	Instruction-Level Parallelism for Reconfigurable Computing.	FPL	1998	DBLP DOI BibTeX RDF
11	Gunter Haug, Wolfgang Rosenstiel	Reconfigurable Hardware as Shared Resource for Parallel Threads.	FCCM	1998	DBLP DOI BibTeX RDF
11	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
11	Alex R. Bugeja, W. Yang	A reconfigurable VLSI coprocessing system for the block matching algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
11	Ram Kesavan, Dhabaleswar K. Panda 0001	Optimal Multicast with Packetization and Network Interface Support.	ICPP	1997	DBLP DOI BibTeX RDF	Network Interface Support and Packetization, Multicast, Interconnection Network, Broadcast, Wormhole Routing, Collective communication, Networks of Workstations, Link Contention
11	Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard	Programmable active memories: reconfigurable systems come of age.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
11	Bonifacio Martín-del-Brío, Javier Blasco-Alberto	Hardware-Oriented Models for VLSI Implementation of Self-Organizing Maps.	IWANN	1995	DBLP DOI BibTeX RDF
11	Stephen D. Scott 0001, Ashok Samal, Sharad C. Seth	HGA: A Hardware-Based Genetic Algorithm.	FPGA	1995	DBLP DOI BibTeX RDF	performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms
11	Peter Soderquist, Miriam Leeser	An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Newton-Raphson method, Goldschmidt's algorithm, microprocessor, Floating-point, division, square root, SRT
11	H. A. Chow, Hussein M. Alnuweiri, Steve Casselman	FPGA-based transformable computers for fast digital signal processing.	FCCM	1995	DBLP DOI BibTeX RDF
11	Ulrich Holtmann, Rolf Ernst	Experiments with low-level speculative computation based on multiple branch prediction.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
11	Myung Hoon Sunwoo, J. K. Aggarwal	A Sliding Memory Plane Array Processor.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures
11	Klaus Gaedke, Hartwig Jeschke, Peter Pirsch	A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
11	Rajesh K. Gupta 0001, Giovanni De Micheli	Hardware-Software Cosynthesis for Digital Systems.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
11	Kam-Fai Wong, M. Howard Williams	CLARE - A Prolog Database Machine.	SIGSMALL/PC Symposium	1990	DBLP DOI BibTeX RDF	Prolog
11	Fadi N. Sibai, Karan L. Watson, Mi Lu	Design and performance measurements of a parallel machine for the unification algorithm.	MICRO	1989	DBLP DOI BibTeX RDF
11	Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson	RISCs versus CISCs for Prolog: A Case Study.	ASPLOS	1987	DBLP DOI BibTeX RDF	Prolog, RISC, CISC