Search results for "loop"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Cameron T. Charles, David J. Allstot	A 360° extended range phase detector for type-I PLLs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Yu Lin, Vipul Katyal, Randall L. Geiger	Power dependence of feedback amplifiers on opamp architecture.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
15	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Optimizing Nested Loops with Iterational and Instructional Retiming.	EUC	2005	DBLP DOI BibTeX RDF
15	Aaron R. Bradley, Zohar Manna, Henny B. Sipma	Termination Analysis of Integer Linear Loops.	CONCUR	2005	DBLP DOI BibTeX RDF
15	Regimantas Pliuskevicius, Aida Pliuskeviciene	Decision Procedure for a Fragment of Mutual Belief Logic with Quantified Agent Variables.	CLIMA	2005	DBLP DOI BibTeX RDF
15	Tze Meng Low, Robert A. van de Geijn, Field G. Van Zee	Extracting SMP parallelism for dense linear algebra algorithms from high-level specifications.	PPoPP	2005	DBLP DOI BibTeX RDF	SMP Parallelism, code generation, linear algebra, formal derivation
15	Asier Ibeas, Manuel de la Sen, Santiago Alonso-Quesada	Intelligent Control of Discrete Linear Systems Based on a Supervised Adaptive Multiestimation Scheme.	J. Intell. Robotic Syst.	2004	DBLP DOI BibTeX RDF	switching techniques, multiestimation, discrete adaptive control, stability, supervisory control
15	Wern-Ho Sheen, Ming-Jou Chang, Cheng-Shong Wu	Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
15	Xuandong Li, Jianhua Zhao, Tao Zheng, Yong Li 0005, Guoliang Zheng	Duration-constrained regular expressions.	Formal Aspects Comput.	2004	DBLP DOI BibTeX RDF	Regular expressions, Hybrid automata, Duration Calculus
15	Lifeng Sha, Xiaoou Tang	Combining exclusive and continuous fingerprint classification.	ICIP	2004	DBLP DOI BibTeX RDF
15	Ke Fu, James K. Mills, Dong Sun 0001	Integrated Design of a Linear Positioning System with Applications to Electronic Manufacturing.	ICRA	2004	DBLP DOI BibTeX RDF
15	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal	Instruction buffering exploration for low energy VLIWs with instruction clusters.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	Tien-Fu Lu, Daniel C. Handley, Yuen Kuan Yong	Position control of a 3 DOF compliant micro-motion stage.	ICARCV	2004	DBLP DOI BibTeX RDF
15	Patrick Carribault, Albert Cohen 0001	Applications of storage mapping optimization to register promotion.	ICS	2004	DBLP DOI BibTeX RDF	array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion
15	Preeti R. Bajaj, Avinash G. Keskar	Exploring Benefits of Neuro Fuzzy Controller with Vehicle Health Monitoring.	KES	2004	DBLP DOI BibTeX RDF
15	Manuel Arenaz, Juan Touriño, Ramon Doallo	An Inspector-Executor Algorithm for Irregular Assignment Parallelization.	ISPA	2004	DBLP DOI BibTeX RDF
15	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Timing Optimization of Nested Loops Considering Code Size for DSP Applications.	ICPP	2004	DBLP DOI BibTeX RDF
15	Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen	Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors.	DATE	2003	DBLP DOI BibTeX RDF
15	Timothy S. Gegg-Harrison, Gary R. Bunce, Rebecca D. Ganetzky, Christina M. Olson, Joshua D. Wilson	Studying program correctness in ProVIDE.	ITiCSE	2003	DBLP DOI BibTeX RDF
15	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
15	Qingguang Huang, Jingling Xue, Xavier Vera	Code Tiling for Improving the Cache Performance of PDE Solvers.	ICPP	2003	DBLP DOI BibTeX RDF
15	Jong-Hyuk Kim, Salah Sukkarieh, Stuart Wishart	Real-Time Navigation, Guidance, and Control of a UAV Using Low-Cost Sensors.	FSR	2003	DBLP DOI BibTeX RDF
15	Johann Blieberger, Bernd Burgstaller, Bernhard Scholz	Busy Wait Analysis.	Ada-Europe	2003	DBLP DOI BibTeX RDF
15	Minyi Guo, Zhen Liu, Chengfei Liu, Li Li 0012	Reducing Communication Cost for Parallelizing Irregular Scientific Codes.	PARA	2002	DBLP DOI BibTeX RDF
15	Éric Colin de Verdière, Francis Lazarus	Optimal System of Loops on an Orientable Surface.	FOCS	2002	DBLP DOI BibTeX RDF
15	Asier Ibeas, Manuel de la Sen, Santiago Alonso-Quesada	A supervised multiestimation scheme for discrete adaptive control.	ICARCV	2002	DBLP DOI BibTeX RDF
15	Chi Ta Wu, TingTing Hwang	Instruction buffering for nested loops in low power design.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Nicholas G. Hall, Chelliah Sriskandarajah, Tharmarajah Ganesharajah	Operational Decisions in AGV-Served Flowshop Loops: Fleet Sizing and Decomposition.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	fleet sizing, decomposition, manufacturing, automated guided vehicles
15	Bharat Chandramouli, John B. Carter, Wilson C. Hsieh, Sally A. McKee	A Cost Framework for Evaluating Integrated Restructuring Optimizations.	IEEE PACT	2001	DBLP DOI BibTeX RDF
15	Matthew C. Merten, Wen-mei W. Hwu	Modulo schedule buffers.	MICRO	2001	DBLP DOI BibTeX RDF
15	Artour Stoutchinin, José Nelson Amaral, Guang R. Gao, James C. Dehnert, Suneel Jain, Alban Douillet	Speculative Prefetching of Induction Pointers.	CC	2001	DBLP DOI BibTeX RDF
15	Siddhartha Chatterjee, Erin Parker, Philip J. Hanlon, Alvin R. Lebeck	Exact Analysis of the Cache Behavior of Nested Loops.	PLDI	2001	DBLP DOI BibTeX RDF
15	Santosh Pande, Tareq Bali	A Compilation Method for Communication-Efficient Partitioning of DOALL Loops.	Compiler Optimizations for Scalable Parallel Systems Languages	2001	DBLP DOI BibTeX RDF
15	Jinghui Lu, Bernard Grung, Stephen Anderson, Shahriar Rokhsaz	Discrete z-domain analysis of high order phase locked loops.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Kuei-Ping Shih, Jang-Ping Sheu, Chua-Huang Huang	Statement-Level Communication-Free Partitioning Techniques for Parallelizing Compilers.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	Communication-free, hyperplane partition, parallelizing compilers, data communication, distributed-memory multicomputers
15	Sungdo Moon, Byoungro So, Mary W. Hall	Evaluating Automatic Parallelization in SUIF.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	array privatization, run-time parallelization, shared-memory multiprocessors, Parallelizing compilers, data dependence analysis
15	Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata	A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors.	ICS	2000	DBLP DOI BibTeX RDF
15	Kainam Thomas Wong	Geolocation for partially polarized electromagnetic sources using multiple sparsely and uniformly spaced "spatially stretched vector sensors".	ISCAS (3)	1999	DBLP DOI BibTeX RDF
15	Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam	Compiler Optimizations for I/O-Intensive Computations.	ICPP	1999	DBLP DOI BibTeX RDF
15	Sriram Vajapeyam, P. J. Joseph, Tulika Mitra	Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs.	ISCA	1999	DBLP DOI BibTeX RDF
15	Tarek S. Abdelrahman, Naraig Manjikian, Gary Liu, Sudarsan Tandri	Locality Enhancement for Large-Scale Shared-Memory Multiprocessors.	LCR	1998	DBLP DOI BibTeX RDF
15	Frank L. Lewis	Neural Network Control of Robot Manipulators.	IEEE Expert	1996	DBLP DOI BibTeX RDF
15	Daniel M. Lavery, Wen-mei W. Hwu	Modulo Scheduling of Loops in Control-intensive Non-numeric Programs.	MICRO	1996	DBLP DOI BibTeX RDF	control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling
15	Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee	Eliminating False Loops Caused by Sharing in Control Path.	ISSS	1996	DBLP DOI BibTeX RDF	false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
15	Shih-Hung Kao, Chao-Tung Yang, Shian-Shyong Tseng	Run-Time Parallelization for Loops.	HICSS (1)	1996	DBLP DOI BibTeX RDF
15	Baowen Xu	PIDL / Pascal: A Pascal-oriented Program Interface Description Language And Its Applications.	ACM SIGPLAN Notices	1993	DBLP DOI BibTeX RDF	Pascal
15	Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin	PLS: a scheduler for pipeline synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
15	Shun-Tak Leung, John Zahorjan	Improving the Performance of Runtime Parallelization.	PPoPP	1993	DBLP DOI BibTeX RDF
15	Ebba Thora Hvannberg, Mukkai S. Krishnamoorthy	An object-based parallel programming assistant.	OOPSLA/ECOOP Workshop on Object-based Concurrent Programming	1988	DBLP DOI BibTeX RDF
15	Shlomo Weiss, James E. Smith 0001	A Study of Scalar Compilation Techniques for Pipelined Supercomputers.	ASPLOS	1987	DBLP DOI BibTeX RDF
15	Douglas D. Dunlop, Victor R. Basili	Generalizing Specifications for Uniformly Implemented Loops.	ACM Trans. Program. Lang. Syst.	1985	DBLP DOI BibTeX RDF
15	Alireza Kavianpour, Arthur D. Friedman	Tradeoffs in system level diagnosis of multiprocessor systems.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF
15	Murray Edelberg, L. Robert Schissler	Intelligent memory.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
14	Rui Wang 0007, Vincent K. N. Lau	Closed-loop cross-layer SDMA designs with outdated CSIT.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
14	Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito 0001	On the exploitation of loop-level parallelism in embedded applications.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	multithreading, Multi-cores, vectorization, libraries, programming models, thread-level speculation, parallel loops, system-on-chip (Soc)
14	Martin J. Murillo, Jeff Slipp	Demo abstract: Application of WINTeR industrial testbed to the analysis of closed-loop control systems in wireless sensor networks.	IPSN	2009	DBLP DOI BibTeX RDF
14	Martin Magnusson 0002, Henrik Andreasson, Andreas Nüchter, Achim J. Lilienthal	Appearance-based loop detection from 3D laser data using the normal distributions transform.	ICRA	2009	DBLP DOI BibTeX RDF
14	Fredy Tungadi, Lindsay Kleeman	Loop exploration for SLAM with fusion of advanced sonar features and laser polar scan matching.	IROS	2009	DBLP DOI BibTeX RDF
14	Vignesh Kumar Chandhrasekran, Bhaskar Prasad Rimal, Eunmi Choi, Dugki Min	Hardware-in-the-Loop simulation of UAV non-linear control system of mini-helicopter.	ICHIT	2009	DBLP DOI BibTeX RDF
14	Lélia Blin, Maria Potop-Butucaru, Stephane Rovedakis, Sébastien Tixeuil	A New Self-stabilizing Minimum Spanning Tree Construction with Loop-Free Property.	DISC	2009	DBLP DOI BibTeX RDF
14	Chao-Tung Yang, Lung-Hsing Cheng	Implementation of a Performance-Based Loop Scheduling on Heterogeneous Clusters.	ICA3PP	2009	DBLP DOI BibTeX RDF
14	Javier Ortiz 0002, Arpan Karwal, Vlastimil Masek	PC based multi-phase flow loop sensor calibration.	CCECE	2009	DBLP DOI BibTeX RDF
14	Young-Tae Kim, Heunchul Lee, Seokhwan Park, Inkyu Lee	Optimal precoding for orthogonalized spatial multiplexing in closed-loop MIMO systems.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
14	Iskandar, Adit Kurniawan, Hendry Syaputra	On the evaluation of fixed step closed loop power control for CDMA High Altitude Platforms (HAPs) communication channel.	PIMRC	2008	DBLP DOI BibTeX RDF
14	Mahbubur Rashid, Ioana Banicescu, Ricolindo Cariño	Investigating a Dynamic Loop Scheduling with Reinforcement Learning Approach to Load Balancing in Scientific Applications.	ISPDC	2008	DBLP DOI BibTeX RDF
14	Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.	DATE	2008	DBLP DOI BibTeX RDF
14	Haihe Shi, Dawei Du, Jinyun Xue	Generating Algorithms plus Loop Invariants by Formal Derivation.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF
14	Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberman, Scott A. Mahlke	Uncovering hidden loop level parallelism in sequential applications.	HPCA	2008	DBLP DOI BibTeX RDF
14	Sung Hyun Moon, Heunchul Lee, Young-Tae Kim, Inkyu Lee	A New Efficient Group-Wise Spatial Multiplexing Design for Closed-Loop MIMO Systems.	ICC	2008	DBLP DOI BibTeX RDF
14	Juan Chen 0001, Yong Dong, Xuejun Yang, Panfeng Wang	Energy-Constrained OpenMP Static Loop Scheduling.	HPCC	2008	DBLP DOI BibTeX RDF
14	Chao-Chin Wu, Lien Fu Lai, Po-Hsun Chiu	Parallel Loop Self-Scheduling for Heterogeneous Cluster Systems with Multi-core Computers.	APSCC	2008	DBLP DOI BibTeX RDF
14	Jianfei Dong, Michel Verhaegen	On the equivalence of closed-loop subspace predictive control with LQG.	CDC	2008	DBLP DOI BibTeX RDF
14	Jianfei Dong, Michel Verhaegen	Model free probabilistic design with uncertain Markov parameters identified in closed loop.	CDC	2008	DBLP DOI BibTeX RDF
14	Jan Dimon Bendtsen, Klaus Trangbaek, Jakob Stoustrup	Closed-loop system identification with new sensors.	CDC	2008	DBLP DOI BibTeX RDF
14	Aldo Balestrino, Emanuele Crisostomi, Alberto Landi, Alessandro Menicagli	ARGA loop pairing criteria for multivariable systems.	CDC	2008	DBLP DOI BibTeX RDF
14	Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha	Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.	FPL	2008	DBLP DOI BibTeX RDF
14	Steffen Kalisch, Robert Ringel, Jörg Weigang	Managing WIP and cycle time with the help of Loop Control.	WSC	2008	DBLP DOI BibTeX RDF
14	Ajay Nair, Roman L. Lysecky	Non-intrusive dynamic application profiler for detailed loop execution characterization.	CASES	2008	DBLP DOI BibTeX RDF	nonintrusive, embedded systems, profiling, dynamic optimization
14	Edgar A. Brown, James D. Ross, Richard A. Blum, Stephen P. DeWeerth	Stimulation and recording of neural tissue, closing the loop on the artifact.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang	A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre	Loop-oriented metrics for exploring an application-specific architecture design-space.	ASAP	2008	DBLP DOI BibTeX RDF
14	Ying Tang, David E. Grochowski	An Integrated Design for Human-in-the-Loop Disassembly.	ICNSC	2008	DBLP DOI BibTeX RDF
14	Giovanni Muscato, Giacomo Spampinato, Luciano Cantelli	A closed loop welding controller for a rapid manufacturing process.	ETFA	2008	DBLP DOI BibTeX RDF
14	Laszlo Kis, Gergely Regula, Béla Lantos	Design and hardware-in-the-loop test of the embedded control system of an indoor quadrotor helicopter.	WISES	2008	DBLP DOI BibTeX RDF
14	Harald Devos, Kristof Beyls, Mark Christiaens, Jan M. Van Campenhout, Erik H. D'Hollander, Dirk Stroobandt	Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
14	Giovanni Emanuele Corazza, Stefano Cioni, Roberto Padovani	Application of Closed Loop Resource Allocation for High Data Rate Packet Transmission.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
14	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	Classifying interprocess communication in process network representation of nested-loop programs.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	hybrid classification approach, matrix manipulations, Static analysis, integer linear programming
14	H. Lee, S. Park, I. Lee	Orthogonalized Spatial Multiplexing for Closed-Loop MIMO Systems.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
14	Mohammad Shikh-Bahaei	Joint Optimization Of "Transmission Rate" and "Outer-Loop SNR Target" Adaptation Over Fading Channels.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
14	Prashanth Krishnamurthy, Farshad Khorrami, Tzer Leei Ng	Control design for unmanned sea surface vehicles: hardware-in-the-loop simulator and experimental results.	IROS	2007	DBLP DOI BibTeX RDF
14	Joon Soo Lee, Shivakanth Gutta, Woosoon Yim	Open-loop control of Ionic Polymer Metal Composite (IPMC) based underwater actuator using a network of neural oscillator.	IROS	2007	DBLP DOI BibTeX RDF
14	Mehdi Pirooznia, Arun Rawat, Jack Y. Yang, Mary Qu Yang, Ping Gong 0001, Edward J. Perkins, Youping Deng	An Effective Interwoven Loop Design Application for Two-Channel Microarray Experiments.	BIBE	2007	DBLP DOI BibTeX RDF
14	Nayan R. Samal, Amit Konar, Swagatam Das, Ajith Abraham	A closed loop stability analysis and parameter selection of the Particle Swarm Optimization dynamics for faster convergence.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
14	Michael Chan 0005, Adam Postula, Yong Ding	PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Dafeng Xu, Qing Li 0010, Hong-Bae Jun, Yuliu Chen, Jim Browne, Dimitris Kiritsis	Modeling for closed-loop product information tracking and feedback using wireless technology.	SMC	2007	DBLP DOI BibTeX RDF
14	Paulina Golinska, Marek Fertsch, Jorge Marx Gómez, Joanna Olesków	The Concept of Closed-loop Supply Chain Integration Through Agents-based System.	ITEE	2007	DBLP DOI BibTeX RDF
14	Pieter Harpe, Athon Zanikopoulos, Hans Hegt, Arthur H. M. van Roermund	Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Sheng Xu 0001, Jochen Kruecker, Peter Guion, Neil D. Glossop, Ziv Neeman, Peter L. Choyke, Anurag K. Singh, Bradford J. Wood	Closed-Loop Control in Fused MR-TRUS Image-Guided Prostate Biopsy.	MICCAI (1)	2007	DBLP DOI BibTeX RDF	prostate biopsy, image registration, motion compensation
14	YingZhi Zeng, Baokang Zhao, Jinshu Su, Xia Yan, Zili Shao	A Loop-Based Key Management Scheme for Wireless Sensor Networks.	EUC Workshops	2007	DBLP DOI BibTeX RDF
14	Hamed Aminzadeh, Mohammad Danaie	Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	frequency compensation, stability, design methodology, operational amplifiers, switched-capacitor circuits, settling time