Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Hideki Ando	SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.	MICRO	2019	DBLP DOI BibTeX RDF
17	Mohammadamin Ajdari, Wonsik Lee, Pyeongsu Park, Joonsung Kim, Jangwoo Kim	FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling.	MICRO	2019	DBLP DOI BibTeX RDF
17	Thomas Bourgeat, Ilia A. Lebedev, Andrew Wright, Sizhuo Zhang, Arvind, Srinivas Devadas	MI6: Secure Enclaves in a Speculative Out-of-Order Processor.	MICRO	2019	DBLP DOI BibTeX RDF
17	Berkin Akin, Zeshan A. Chishti, Alaa R. Alameldeen	ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions.	MICRO	2019	DBLP DOI BibTeX RDF
17	Renhai Chen, Zili Shao, Duo Liu, Zhiyong Feng 0002, Tao Li 0006	Towards Efficient NVDIMM-based Heterogeneous Storage Hierarchy Management for Big Data Workloads.	MICRO	2019	DBLP DOI BibTeX RDF
17	Yu Feng 0007, Paul N. Whatmough, Yuhao Zhu 0001	ASV: Accelerated Stereo Vision System.	MICRO	2019	DBLP DOI BibTeX RDF
17	Lucas Morais, Vitor Silva, Alfredo Goldman, Carlos Álvarez 0001, Jaume Bosch, Michael Frank 0008, Guido Araujo	Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor.	MICRO	2019	DBLP DOI BibTeX RDF
17	Mingyu Yan, Xing Hu 0001, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng 0003, Xiaochun Ye, Zhimin Zhang 0004, Dongrui Fan, Yuan Xie 0001	Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.	MICRO	2019	DBLP DOI BibTeX RDF
17	Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang 0013, Li-De Chen	eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference.	MICRO	2019	DBLP DOI BibTeX RDF
17	Pranav Gokhale, Yongshan Ding 0001, Thomas Propson, Christopher Winkler, Nelson Leung, Yunong Shi, David I. Schuster, Henry Hoffmann, Frederic T. Chong	Partial Compilation of Variational Algorithms for Noisy Intermediate-Scale Quantum Machines.	MICRO	2019	DBLP DOI BibTeX RDF
17	Fei Gao 0016, Georgios Tziantzioulis, David Wentzlaff	ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs.	MICRO	2019	DBLP DOI BibTeX RDF
17	Mayank Parasar, Natalie D. Enright Jerger, Paul V. Gratz, Joshua San Miguel, Tushar Krishna	SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution.	MICRO	2019	DBLP DOI BibTeX RDF
17	Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang 0009, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang 0002, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler	Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.	MICRO	2019	DBLP DOI BibTeX RDF
17	Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher	ExTensor: An Accelerator for Sparse Tensor Algebra.	MICRO	2019	DBLP DOI BibTeX RDF
17	Ziqiang Huang, José A. Joao, Alejandro Rico, Andrew D. Hilton, Benjamin C. Lee	DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management.	MICRO	2019	DBLP DOI BibTeX RDF
17	Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev 0001, Nael B. Abu-Ghazaleh, Lei Yu 0001	LATCH: A Locality-Aware Taint CHecker.	MICRO	2019	DBLP DOI BibTeX RDF
17	Mohammad Shahrad, Jonathan Balkind, David Wentzlaff	Architectural Implications of Function-as-a-Service Computing.	MICRO	2019	DBLP DOI BibTeX RDF
17	Jongouk Choi, Qingrui Liu, Changhee Jung	CoSpec: Compiler Directed Speculative Intermittent Computation.	MICRO	2019	DBLP DOI BibTeX RDF
17	Jacob R. Stevens, Ashish Ranjan 0001, Dipankar Das 0002, Bharat Kaul, Anand Raghunathan	Manna: An Accelerator for Memory-Augmented Neural Networks.	MICRO	2019	DBLP DOI BibTeX RDF
17	Eunjin Baek, Hunjun Lee, Youngsok Kim, Jangwoo Kim	FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning.	MICRO	2019	DBLP DOI BibTeX RDF
17	Poulami Das 0005, Swamit S. Tannu, Prashant J. Nair, Moinuddin K. Qureshi	A Case for Multi-Programming Quantum Computers.	MICRO	2019	DBLP DOI BibTeX RDF
17	Zhan Shi, Xiangru Huang, Akanksha Jain, Calvin Lin	Applying Deep Learning to the Cache Replacement Problem.	MICRO	2019	DBLP DOI BibTeX RDF
17	Xiang Fu 0003, M. A. Rol, Cornelis Christiaan Bultink, J. van Someren 0001, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels	A Microarchitecture for a Superconducting Quantum Processor.	IEEE Micro	2018	DBLP DOI BibTeX RDF
17	M. Reza HoseinyFarahabady, Albert Y. Zomaya, Zahir Tari	A Model Predictive Controller for Managing QoS Enforcements and Microarchitecture-Level Interferences in a Lambda Platform.	IEEE Trans. Parallel Distributed Syst.	2018	DBLP DOI BibTeX RDF
17	Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari	A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
17	Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu	Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism.	CoRR	2018	DBLP BibTeX RDF
17	Khaled Harrar, Rachid Jennane, Karima Zaouchi, Thomas Janvier, Hechmi Toumi, Eric Lespessailles	Oriented fractal analysis for improved bone microarchitecture characterization.	Biomed. Signal Process. Control.	2018	DBLP DOI BibTeX RDF
17	Shady O. Agwa, Eslam Yahya, Yehea Ismail	A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
17	Ahmad Yasin, Yosi Ben-Asher	A first-order approximation of microarchitecture energy-efficiency.	SAMOS	2018	DBLP DOI BibTeX RDF
17	Norishige Fukushima, Yoshihiro Maeda, Yuki Kawasaki, Masahiro Nakamura, Tomoaki Tsumura, Kenjiro Sugimoto, Sei-ichiro Kamata	Efficient Computational Scheduling of Box and Gaussian FIR Filtering for CPU Microarchitecture.	APSIPA	2018	DBLP DOI BibTeX RDF
17	Yuze Chi, Peipei Zhou 0001, Jason Cong	An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
17	Johan Laurent, Vincent Beroulle, Christophe Deleuze, Florian Pebay-Peyroula, Athanasios Papadimitriou	On the Importance of Analysing Microarchitecture for Accurate Software Fault Models.	DSD	2018	DBLP DOI BibTeX RDF
17		51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018	MICRO	2018	DBLP BibTeX RDF
17	Huixiang Chen 0001, Yuting Dai, Rui Xue, Kan Zhong, Tao Li 0006	Towards Efficient Microarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality Era.	ICCD	2018	DBLP DOI BibTeX RDF
17	Alessandro Vallero, Sotiris Tselonis, Dimitris Gizopoulos, Stefano Di Carlo	Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUs.	VTS	2018	DBLP DOI BibTeX RDF
17	Michael Brehler, Qian Cao, K. F. Moseley, Greg Osgood, C. Morris, Shadpour Demehri, John Yorkston, Jeffrey H. Siewerdsen, Wojciech Zbijewski	Robust quantitative assessment of trabecular microarchitecture in extremity cone-beam CT using optimized segmentation algorithms.	Medical Imaging: Biomedical Applications in Molecular, Structural, and Functional Imaging	2018	DBLP DOI BibTeX RDF
17	Xing Hu 0001, Matheus Ogleari, Jishen Zhao, Shuangchen Li, Abanti Basak, Yuan Xie 0001	Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.	MICRO	2018	DBLP DOI BibTeX RDF
17	Kartik Hegde, Rohit Agrawal 0001, Yulun Yao, Christopher W. Fletcher	Morph: Flexible Acceleration for 3D CNN-Based Video Understanding.	MICRO	2018	DBLP DOI BibTeX RDF
17	Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer	DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors.	MICRO	2018	DBLP DOI BibTeX RDF
17	Chunhua Deng, Siyu Liao, Yi Xie 0001, Keshab K. Parhi, Xuehai Qian, Bo Yuan 0001	PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices.	MICRO	2018	DBLP DOI BibTeX RDF
17	Sam Silvestro, Hongyu Liu 0005, Tong Zhang, Changhee Jung, Dongyoon Lee, Tongping Liu	Sampler: PMU-Based Sampling to Detect Memory Errors Latent in Production Software.	MICRO	2018	DBLP DOI BibTeX RDF
17	Shuangchen Li, Alvin Oliver Glova, Xing Hu 0001, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie 0001	SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.	MICRO	2018	DBLP DOI BibTeX RDF
17	Anurag Mukkara, Nathan Beckmann, Maleen Abeydeera, Xiaosong Ma, Daniel Sánchez 0003	Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling.	MICRO	2018	DBLP DOI BibTeX RDF
17	Hongyuan Liu 0002, Mohamed Assem Ibrahim, Onur Kayiran, Sreepathi Pai, Adwait Jog	Architectural Support for Efficient Large-Scale Automata Processing.	MICRO	2018	DBLP DOI BibTeX RDF
17	Xingyao Zhang, Chenhao Xie 0001, Jing Wang 0055, Weidong Zhang, Xin Fu	Towards Memory Friendly Long-Short Term Memory Networks (LSTMs) on Mobile GPUs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Pengfei Zuo, Yu Hua 0001, Ming Zhao 0002, Wen Zhou, Yuncheng Guo	Improving the Performance and Endurance of Encrypted Non-Volatile Main Memory through Deduplicating Writes.	MICRO	2018	DBLP DOI BibTeX RDF
17	Dani Voitsechov, Oron Port, Yoav Etsion	Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays.	MICRO	2018	DBLP DOI BibTeX RDF
17	Jungi Jeong, Chang Hyun Park 0001, Jaehyuk Huh 0001, Seungryoul Maeng	Efficient Hardware-Assisted Logging with Asynchronous and Direct-Update for Persistent Memory.	MICRO	2018	DBLP DOI BibTeX RDF
17	Emre Ozer 0001, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton	Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems.	MICRO	2018	DBLP DOI BibTeX RDF
17	Byungchul Hong, Yeonju Ro, John Kim	Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture.	MICRO	2018	DBLP DOI BibTeX RDF
17	Xuda Zhou, Zidong Du, Qi Guo 0001, Shaoli Liu, Chengsi Liu, Chao Wang 0003, Xuehai Zhou, Ling Li 0001, Tianshi Chen 0002, Yunji Chen	Cambricon-S: Addressing Irregularity in Sparse Neural Networks through A Cooperative Software/Hardware Approach.	MICRO	2018	DBLP DOI BibTeX RDF
17	Hanhwi Jang, Jae-Eon Jo, Jaewon Lee, Jangwoo Kim	RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors.	MICRO	2018	DBLP DOI BibTeX RDF
17	Joonsung Kim, Pyeongsu Park, Jaehyung Ahn, Jihun Kim 0002, Jong Kim 0001, Jangwoo Kim	SSDcheck: Timely and Accurate Prediction of Irregular Behaviors in Black-Box SSDs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Esha Choukse, Mattan Erez, Alaa R. Alameldeen	Compresso: Pragmatic Main Memory Compression.	MICRO	2018	DBLP DOI BibTeX RDF
17	Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, Michael B. Healy	Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.	MICRO	2018	DBLP DOI BibTeX RDF
17	Amna Shahab, Mingcan Zhu, Artemiy Margaritov, Boris Grot	Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers.	MICRO	2018	DBLP DOI BibTeX RDF
17	Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, José A. Joao, Moinuddin K. Qureshi	Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.	MICRO	2018	DBLP DOI BibTeX RDF
17	Xian Zhang 0001, Guangyu Sun 0003, Peichen Xie, Chao Zhang 0007, Yannan Liu, Lingxiao Wei, Qiang Xu 0001, Chun Jason Xue	Shadow Block: Accelerating ORAM Accesses with Data Duplication.	MICRO	2018	DBLP DOI BibTeX RDF
17	Po-An Tsai, Yee Ling Gan, Daniel Sánchez 0003	Rethinking the Memory Hierarchy for Modern Languages.	MICRO	2018	DBLP DOI BibTeX RDF
17	Haiyu Mao, Mingcong Song, Tao Li 0006, Yuting Dai, Jiwu Shu	LerGAN: A Zero-Free, Low Data Movement and PIM-Based GAN Architecture.	MICRO	2018	DBLP DOI BibTeX RDF
17	Almutaz Adileh, David J. Lilja, Lieven Eeckhout	Architectural Support for Probabilistic Branches.	MICRO	2018	DBLP DOI BibTeX RDF
17	Yunho Oh, Myung Kuk Yoon, William J. Song, Won Woo Ro	FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput.	MICRO	2018	DBLP DOI BibTeX RDF
17	Sumitha George, Minli Julie Liao, Huaipan Jiang, Jagadish B. Kotra, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan	MDACache: Caching for Multi-Dimensional-Access Memories.	MICRO	2018	DBLP DOI BibTeX RDF
17	Seunghee Shin, Michael LeBeane, Yan Solihin, Arkaprava Basu	Neighborhood-Aware Address Translation for Irregular GPU Applications.	MICRO	2018	DBLP DOI BibTeX RDF
17	Farzad Khorasani, Hodjat Asghari Esfeden, Nael B. Abu-Ghazaleh, Vivek Sarkar	In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization.	MICRO	2018	DBLP DOI BibTeX RDF
17	Sizhuo Zhang, Andrew Wright, Thomas Bourgeat, Arvind	Composable Building Blocks to Open up Processor Design.	MICRO	2018	DBLP DOI BibTeX RDF
17	Mengjia Yan 0001, Jiho Choi, Dimitrios Skarlatos 0002, Adam Morrison 0001, Christopher W. Fletcher, Josep Torrellas	InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy.	MICRO	2018	DBLP DOI BibTeX RDF
17	Jiawen Liu, Hengyu Zhao, Matheus A. Ogleari, Dong Li 0001, Jishen Zhao	Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach.	MICRO	2018	DBLP DOI BibTeX RDF
17	Joshua San Miguel, Karthik Ganesan 0002, Mario Badr, Chunqiu Xia, Rose Li, Hsuan Hsiao, Natalie D. Enright Jerger	The EH Model: Early Design Space Exploration of Intermittent Processor Architectures.	MICRO	2018	DBLP DOI BibTeX RDF
17	Shenghsun Cho, Amoghavarsha Suresh, Tapti Palit, Michael Ferdman, Nima Honarmand	Taming the Killer Microsecond.	MICRO	2018	DBLP DOI BibTeX RDF
17	Behzad Boroujerdian, Hasan Genc, Srivatsan Krishnan, Wenzhi Cui, Aleksandra Faust, Vijay Janapa Reddi	MAVBench: Micro Aerial Vehicle Benchmarking.	MICRO	2018	DBLP DOI BibTeX RDF
17	Tri Minh Nguyen 0003, Adi Fuchs, David Wentzlaff	CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores.	MICRO	2018	DBLP DOI BibTeX RDF
17	Youjie Li, Jongse Park, Mohammad Alian, Yifan Yuan, Zheng Qu 0002, Peitian Pan, Ren Wang 0001, Alexander G. Schwing, Hadi Esmaeilzadeh, Nam Sung Kim	A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks.	MICRO	2018	DBLP DOI BibTeX RDF
17	An Zou, Jingwen Leng, Xin He, Yazhou Zu, Christopher D. Gill, Vijay Janapa Reddi, Xuan Zhang 0001	Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Prasanna Venkatesh Rengasamy, Haibo Zhang 0005, Shulin Zhao 0001, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das	CritICs Critiquing Criticality in Mobile Apps.	MICRO	2018	DBLP DOI BibTeX RDF
17	Hideki Ando	Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.	MICRO	2018	DBLP DOI BibTeX RDF
17	Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta	PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications.	MICRO	2018	DBLP DOI BibTeX RDF
17	Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David W. Nellans, Oreste Villa	Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems.	MICRO	2018	DBLP DOI BibTeX RDF
17	Donghyun Gouk, Miryeong Kwon, Jie Zhang 0048, Sungjoon Koh, Wonil Choi, Nam Sung Kim, Mahmut T. Kandemir, Myoungsoo Jung	Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources.	MICRO	2018	DBLP DOI BibTeX RDF
17	Moumita Dey, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic	EMPROF: Memory Profiling Via EM-Emanation in IoT and Hand-Held Devices.	MICRO	2018	DBLP DOI BibTeX RDF
17	Bin Nie, Lishan Yang, Adwait Jog, Evgenia Smirni	Fault Site Pruning for Practical Reliability Analysis of GPGPU Applications.	MICRO	2018	DBLP DOI BibTeX RDF
17	Tri Minh Nguyen 0003, David Wentzlaff	PiCL: A Software-Transparent, Persistent Cache Log for Nonvolatile Main Memory.	MICRO	2018	DBLP DOI BibTeX RDF
17	Qingrui Liu, Joseph Izraelevitz, Se Kwon Lee, Michael L. Scott, Sam H. Noh, Changhee Jung	iDO: Compiler-Directed Failure Atomicity for Nonvolatile Memory.	MICRO	2018	DBLP DOI BibTeX RDF
17	Hidetsugu Irie, Toru Koizumi 0001, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai	STRAIGHT: Hazardless Processor Architecture Without Register Renaming.	MICRO	2018	DBLP DOI BibTeX RDF
17	Youwei Zhuo, Jinglei Cheng, Qinyi Luo, Jidong Zhai, Yanzhi Wang, Zhongzhi Luan, Xuehai Qian	CSE: Parallel Finite State Machines with Convergence Set Enumeration.	MICRO	2018	DBLP DOI BibTeX RDF
17	Kevin Angstadt, Arun Subramaniyan 0001, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das	ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata.	MICRO	2018	DBLP DOI BibTeX RDF
17	Jagadish B. Kotra, Haibo Zhang 0005, Alaa R. Alameldeen, Chris Wilkerson, Mahmut T. Kandemir	CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System.	MICRO	2018	DBLP DOI BibTeX RDF
17	Wonil Choi, Myoungsoo Jung, Mahmut T. Kandemir	Invalid Data-Aware Coding to Enhance the Read Performance of High-Density Flash Memories.	MICRO	2018	DBLP DOI BibTeX RDF
17	Yongshan Ding 0001, Adam Holmes, Ali Javadi-Abhari, Diana Franklin, Margaret Martonosi, Frederic T. Chong	Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures.	MICRO	2018	DBLP DOI BibTeX RDF
17	Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez 0003	Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism.	MICRO	2018	DBLP DOI BibTeX RDF
17	Behzad Salami 0001, Osman S. Unsal, Adrián Cristal Kestelman	Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories.	MICRO	2018	DBLP DOI BibTeX RDF
17	Mao Ye, Clayton Hughes, Amro Awad	Osiris: A Low-Cost Mechanism to Enable Restoration of Secure Non-Volatile Memories.	MICRO	2018	DBLP DOI BibTeX RDF
17	Youngeun Kwon, Minsoo Rhu	Beyond the Memory Wall: A Case for Memory-Centric HPC System for Deep Learning.	MICRO	2018	DBLP DOI BibTeX RDF
17	Po-An Tsai, Changping Chen, Daniel Sánchez 0003	Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies.	MICRO	2018	DBLP DOI BibTeX RDF
17	Da Zhang 0004, Vilas Sridharan, Xun Jian 0002	Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Mostafa Mahmoud, Kevin Siu, Andreas Moshovos	Diffy: a Déjà vu-Free Differential Deep Neural Network Accelerator.	MICRO	2018	DBLP DOI BibTeX RDF
17	Alberto Ros 0001, Stefanos Kaxiras	The Superfluous Load Queue.	MICRO	2018	DBLP DOI BibTeX RDF
17	Steve Margerm, Amirali Sharifian, Apala Guha, Arrvindh Shriraman, Gilles Pokam	TAPAS: Generating Parallel Accelerators from Parallel Programs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Mohammad Alian, Seungwon Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam J. McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-Mei W. Hwu, Nam Sung Kim	Application-Transparent Near-Memory Processing Architecture with Memory Channel Network.	MICRO	2018	DBLP DOI BibTeX RDF
17	Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides	Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization.	MICRO	2018	DBLP DOI BibTeX RDF