|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 4401 occurrences of 2030 keywords
|
|
|
Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Chun-hong Chen, Chi-Ying Tsui |
Towards the capability of providing power-area-delay trade-off at the register transfer level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 24-29, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Laurence Tianruo Yang, Zebo Peng |
An Improved Register-Transfer Level Functional Partitioning Approach for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10107-, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Randall J. Fisher, Henry G. Dietz |
Compiling for SIMD Within a Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 11th International Workshop, LCPC'98, Chapel Hill, NC, USA, August 7-9, 1998, Proceedings, pp. 290-304, 1998, Springer, 3-540-66426-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Sandeep Agarwal, Fayez El Guibaly |
Modeling of Shift Register-based ATM Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 146-151, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Kazuhito Ito, Keshab K. Parhi |
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(1), pp. 57-72, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Keith D. Cooper, John Lu |
Register Promotion in C Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), Las Vegas, Nevada, USA, June 15-18, 1997, pp. 308-319, 1997, ACM, 0-89791-907-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
C |
16 | Catherine H. Gebotys |
Low Energy Memory and Register Allocation Using Network Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 435-440, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Fermín Sánchez, Jordi Cortadella |
RESIS: A New Methodology for Register Optimization in Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 824-832, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Krzysztof Diks, Torben Hagerup |
More General Parallel Tree Contraction: Register Allocation and Broadcasting in a Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WG ![In: Graph-Theoretic Concepts in Computer Science, 22nd International Workshop, WG '96, Cadenabbia (Como), Italy, June 12-14, 1996, Proceedings, pp. 126-140, 1996, Springer, 3-540-62559-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Johannes Steensma, Francky Catthoor, Hugo De Man |
Partial scan and symbolic test at the register-transfer level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 7-23, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes |
16 | Chen-Yi Lee, Jer-Min Tsai |
A shift register architecture for high-speed data sorting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 11(3), pp. 273-280, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Ashok Sudarsanam, Sharad Malik |
Memory bank and register allocation in software synthesis for ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 388-392, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | John A. Nestor |
Visual register-transfer description of VLSI microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(1), pp. 72-76, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential test generation and synthesis for testability at the register-transfer and logic levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 579-598, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Allen C.-H. Wu, Daniel D. Gajski |
Partitioning algorithms for layout synthesis from register-transfer netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 453-463, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Miodrag J. Mihaljevic, Jovan Dj. Golic |
Convergence of a Bayesian Iterative Error-Correction Procedure on a Noisy Shift register Sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '92, Workshop on the Theory and Application of of Cryptographic Techniques, Balatonfüred, Hungary, May 24-28, 1992, Proceedings, pp. 124-137, 1992, Springer, 3-540-56413-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Algorithms, Cryptanalysis, Convergence, Decoding, Shift registers, Fast correlation attack |
16 | Michael Merritt, Gadi Taubenfeld |
Atomic m-Register Operations (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 5th International Workshop, WDAG '91, Delphi, Greece, October 7-9, 1991, Proceedings, pp. 289-294, 1991, Springer, 3-540-55236-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka |
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings, pp. 76-85, 1990, Springer, 3-540-54477-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Gary J. Murakami, Roy H. Campbell, Michael Faiman |
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM Symposium on Communications Architectures & Protocols, SIGCOMM 1990, Philadelpia, PA, USA, September 24-27, 1990, pp. 145-155, 1990, ACM, 0-89791-405-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Miodrag J. Mihaljevic, Jovan Dj. Golic |
A Fast Iterative Algorithm For A Shift Register Initial State Reconstruction Given The Nosiy Output Sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AUSCRYPT ![In: Advances in Cryptology - AUSCRYPT '90, International Conference on Cryptology, Sydney, Australia, January 8-11, 1990, Proceedings, pp. 165-175, 1990, Springer, 3-540-53000-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | David Callahan, Steve Carr 0001, Ken Kennedy |
Improving register allocation for subscripted variables (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 328-342, 1990, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | David Callahan, Steve Carr 0001, Ken Kennedy |
Improving Register Allocation for Subscripted Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 53-65, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
FORTRAN |
16 | Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong |
Simulation based verification of register-transfer level behavioral synthesis tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 396-400, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Ranga Vemuri |
On the notion of the normal form register-level structures and its applications in design-space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 46-51, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Jovan Dj. Golic, Miodrag J. Mihaljevic |
A Noisy Clock-Controlled Shift Register Cryptanalysis Concept Based on Sequence Comparion Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '90, Workshop on the Theory and Application of of Cryptographic Techniques, Aarhus, Denmark, May 21-24, 1990, Proceedings, pp. 487-491, 1990, Springer, 3-540-53587-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Salvatore Filippone, Paolo Santangelo, Marcello Vitaletti |
A vectorized long-period shift-register random number generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 676-684, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
FORTRAN |
16 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential Test Generation at the Register-Transfer and Logic Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 580-586, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Preston Briggs, Keith D. Cooper, Ken Kennedy, Linda Torczon |
Coloring Heuristics for Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'89 Conference on Programming Language Design and Implementation (PLDI), Portland, Oregon, USA, June 21-23, 1989, pp. 275-284, 1989, ACM, 0-89791-306-X. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
FORTRAN |
16 | Preston Briggs, Keith D. Cooper, Ken Kennedy, Linda Torczon |
Coloring heuristics for register allocation (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 283-294, 1989, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Réjane Forré |
A Fats Correlation Attack on Nonlinearly Feedforward Filtered Shift-Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '89, Workshop on the Theory and Application of of Cryptographic Techniques, Houthalen, Belgium, April 10-13, 1989, Proceedings, pp. 586-595, 1989, Springer, 3-540-53433-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Gert Goossens, Joos Vandewalle, Hugo De Man |
Loop Optimization in Register-Transfer Scheduling for DSP-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 826-831, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Fadi J. Kurdahi, Alice C. Parker |
REAL: a program for REgister ALlocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 210-215, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
16 | James R. Larus, Paul N. Hilfinger |
Register allocation in the SPUR Lisp compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the 1986 SIGPLAN Symposium on Compiler Construction, Palo Alto, California, USA, June 25-27, 1986, pp. 255-263, 1986, ACM, 0-89791-197-0. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
LISP, LISP |
16 | Harald Niederreiter |
A Public-Key Cryptosystem based on Shift Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '85, Workshop on the Theory and Application of of Cryptographic Techniques, Linz, Austria, April 1985, Proceedings, pp. 35-39, 1985, Springer, 3-540-16468-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Tore Herlestam |
On Functions of Linear Shift Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '85, Workshop on the Theory and Application of of Cryptographic Techniques, Linz, Austria, April 1985, Proceedings, pp. 119-129, 1985, Springer, 3-540-16468-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Ted G. Lewis, William H. Payne |
Generalized Feedback Shift Register Pseudorandom Number Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 20(3), pp. 456-468, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
16 | Lawrence Paul Horwitz, Richard M. Karp, Raymond E. Miller, Shmuel Winograd |
Index Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 13(1), pp. 43-61, 1966. The full citation details ...](Pics/full.jpeg) |
1966 |
DBLP DOI BibTeX RDF |
|
15 | Amit Golander, Shlomo Weiss |
Checkpoint allocation and release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 10:1-10:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback |
15 | Sandrine Blazy, Benoît Robillard |
Live-range unsplitting for faster optimal coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 70-79, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
register allocation, graph reduction, coalescing |
15 | Andreas Larsson, Anders Gidenstam, Phuong Hoai Ha, Marina Papatriantafilou, Philippas Tsigas |
Multiword atomic read/write registers on multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Exp. Algorithmics ![In: ACM J. Exp. Algorithmics 13, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
synchronization, wait-free, Atomic register |
15 | Thomas Kotzmann, Christian Wimmer, Hanspeter Mössenböck, Thomas Rodriguez, Kenneth B. Russell, David Cox |
Design of the Java HotSpot™ client compiler for Java 6. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(1), pp. 7:1-7:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
deoptimization, Java, optimization, compiler, register allocation, just-in-time compilation, intermediate representation |
15 | Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao |
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 209-223, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register organization, VLIW, digital signal processor, micro-architecture, instruction encoding |
15 | Xuejun Yang, Ying Zhang 0032, Jingling Xue, Ian Rogers, Gen Li 0002, Guibin Wang |
Exploiting loop-dependent stream reuse for stream processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 22-31, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
StreamC, stream professor, stream register file, stream reuse, stream programming model |
15 | Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi |
Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 7th IEEE/ACIS International Conference on Computer and Information Science, IEEE/ACIS ICIS 2008, 14-16 May 2008, Portland, Oregon, USA, pp. 33-38, 2008, IEEE Computer Society, 978-0-7695-3131-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing |
15 | Ricky Yiu-kee Choi, Chi-Ying Tsui |
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 317-320, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Successive Approximation Register ADC, Low Power |
15 | Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham |
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1401-1414, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit |
15 | Mathias Ortner, Xavier Descombes, Josiane Zerubia |
Building Outline Extraction from Digital Elevation Models Using Marked Point Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 72(2), pp. 107-132, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
inhomogeneous Poisson point process, dense urban area, laser data, land register, RJMCMC, image processing, simulated annealing, MCMC, stochastic geometry, digital elevation models, building detection |
15 | Daniel J. Bernstein, Tanja Lange 0001 |
Faster Addition and Doubling on Elliptic Curves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT 2007, 13th International Conference on the Theory and Application of Cryptology and Information Security, Kuching, Malaysia, December 2-6, 2007, Proceedings, pp. 29-50, 2007, Springer, 978-3-540-76899-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-scalar multiplication, side-channel countermeasures, unified addition formulas, complete addition formulas, performance evaluation, Elliptic curves, register allocation, scalar multiplication, efficient implementation, addition, explicit formulas, doubling |
15 | Weijia Li, Youtao Zhang, Jun Yang 0002, Jiang Zheng 0002 |
UCC: update-conscious compilation for energy efficiency in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 383-393, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sensor networks, register allocation, code dissemination |
15 | Soheil Aminzadeh, Saeed Safari |
Co-evolutionary high-level test synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 67-72, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
co-evolutionary algorithm, module binding, genetic algorithm, scheduling, register allocation, high-level test synthesis |
15 | Joel David Hamkins, David Linetsky, Russell G. Miller |
The Complexity of Quickly ORM-Decidable Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CiE ![In: Computation and Logic in the Real World, Third Conference on Computability in Europe, CiE 2007, Siena, Italy, June 18-23, 2007, Proceedings, pp. 488-496, 2007, Springer, 978-3-540-73000-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ordinal computation, infinite time computation, hyperarithmetical hierarchy, complexity, computability, Ordinal, arithmetical hierarchy, register machine |
15 | Alex Gontmakher, Avi Mendelson, Assaf Schuster |
Using fine grain multithreading for energy efficient computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2007, San Jose, California, USA, March 14-17, 2007, pp. 259-269, 2007, ACM, 978-1-59593-602-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register sharing, energy efficiency, fine grain parallelization |
15 | Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope |
Supporting Microthread Scheduling and Synchronisation in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(4), pp. 343-381, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Microgrids, microthreads, schedulers, CMPs, register files |
15 | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
Offset assignment using simultaneous variable coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(4), pp. 864-883, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation |
15 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 123-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers |
15 | George Petrides, Johannes Mykkeltveit |
On the Classification of Periodic Binary Sequences into Nonlinear Complexity Classes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 209-222, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nonlinear complexity, short cycles, nonlinear feedback shift register |
15 | Bin Zhang 0003, Dengguo Feng |
New Guess-and-Determine Attack on the Self-Shrinking Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT 2006, 12th International Conference on the Theory and Application of Cryptology and Information Security, Shanghai, China, December 3-7, 2006, Proceedings, pp. 54-68, 2006, Springer, 3-540-49475-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Self-shrinking, Guess-and-determine, Stream cipher, Linear feedback shift register (LFSR) |
15 | Dongwon Jeong, Youn-Hee Han |
Resolving the Semantic Inconsistency Problem for Ubiquitous RFID Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UIC ![In: Ubiquitous Intelligence and Computing, Third International Conference, UIC 2006, Wuhan, China, September 3-6, 2006, Proceedings, pp. 1134-1143, 2006, Springer, 3-540-38091-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Metadata register, Ubiquitous computing, Semantic, Interoperability, RFID, Consistency |
15 | Michel Raynal, Corentin Travers |
In Search of the Holy Grail: Looking for the Weakest Failure Detector for Wait-Free Set Agreement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 10th International Conference, OPODIS 2006, Bordeaux, France, December 12-15, 2006, Proceedings, pp. 3-19, 2006, Springer, 3-540-49990-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Leader oracle, Participating process, Consensus, Asynchronous system, Shared object, Atomic register, Set agreement, Asynchronous algorithm, Wait-free algorithm |
15 | Yi-Bing Lin |
Per-User Checkpointing for Mobility Database Failure Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 4(2), pp. 189-194, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
failure restoration, Checkpoint, Universal Mobile Telecommunications System (UMTS), General Packet Radio Service (GPRS), Home Location Register |
15 | Weiwu Hu, Fuxin Zhang, Zusong Li |
Microarchitecture of the Godson-2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 243-249, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming |
15 | François Panneton, Pierre L'Ecuyer |
On the xorshift random number generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Model. Comput. Simul. ![In: ACM Trans. Model. Comput. Simul. 15(4), pp. 346-361, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
linear recurrence modulo 2, xorshift, linear feedback shift register, Random number generation |
15 | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
Instruction set extension with shadow registers for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 99-106, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
shadow register, compilation, ASIP, configurable processor |
15 | Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Hong Wang |
Weaknesses of COSvd (2, 128) Stream Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2005, 8th International Conference, Seoul, Korea, December 1-2, 2005, Revised Selected Papers, pp. 270-283, 2005, Springer, 3-540-33354-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
COS cipher, Non- linear feedback shift register, Stream cipher, Divide-and-Conquer |
15 | Hyun-Gyu Kim, Hyeong-Cheol Oh |
A DSP-Enhanced 32-Bit Embedded Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 17-26, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD |
15 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 50-55, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
15 | Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001 |
A Fast Correlation Attack on the Shrinking Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2005, The Cryptographers' Track at the RSA Conference 2005, San Francisco, CA, USA, February 14-18, 2005, Proceedings, pp. 72-86, 2005, Springer, 3-540-24399-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Linear feedback shift register, Fast correlation attack, Shrinking generator |
15 | Bogdan S. Chlebus, Dariusz R. Kowalski |
Cooperative asynchronous update of shared memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 37th Annual ACM Symposium on Theory of Computing, Baltimore, MD, USA, May 22-24, 2005, pp. 733-739, 2005, ACM, 1-58113-960-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
problem Write-All, read and write register, work efficiency, distributed algorithm, expander, asynchrony, disperser |
15 | Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan |
Power emulation: a new paradigm for power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 700-705, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels |
15 | Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov |
Architecture-aware classical Taylor shift by 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSAC ![In: Symbolic and Algebraic Computation, International Symposium ISSAC 2005, Beijing, China, July 24-27, 2005, Proceedings, pp. 200-207, 2005, ACM, 1-59593-095-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling |
15 | Dmitri Bronnikov |
A practical adoption of partial redundancy elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 39(8), pp. 49-53, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
partial redundancy elimination, register spilling |
15 | Jin Lin, Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan |
A compiler framework for speculative optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(3), pp. 247-271, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
speculative SSA form, speculative weak update, partial redundancy elimination, Data speculation, register promotion |
15 | Mayur Naik, Jens Palsberg |
Compiling with code-size constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(1), pp. 163-181, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Banked architecture, register allocation, integer linear programming, space optimization |
15 | Kellie Michele Evans |
Is Bosco's Rule Universal? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCU ![In: Machines, Computations, and Universality, 4th International Conference, MCU 2004, Saint Petersburg, Russia, September 21-24, 2004, Revised Selected Papers, pp. 188-199, 2004, Springer, 3-540-25261-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
gliders, Larger than Life, sliding block memory, spaceships, cellular automata, universal, bugs, register, Game of Life |
15 | Carole Delporte-Gallet, Hugues Fauconnier, Rachid Guerraoui, Vassos Hadzilacos, Petr Kouznetsov, Sam Toueg |
The weakest failure detectors to solve certain fundamental problems in distributed computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Third Annual ACM Symposium on Principles of Distributed Computing, PODC 2004, St. John's, Newfoundland, Canada, July 25-28, 2004, pp. 338-346, 2004, ACM, 1-58113-802-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
non-blocking atomic commit, quittable consensus, weakest failure detector, consensus, register |
15 | Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001 |
Chosen Ciphertext Attack on a New Class of Self-Synchronizing Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2004, 5th International Conference on Cryptology in India, Chennai, India, December 20-22, 2004, Proceedings, pp. 73-83, 2004, Springer, 3-540-24130-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
2-adic expansion, Stream cipher, Self-synchronizing, Feedback shift register |
15 | Xinmiao Zhang, Keshab K. Parhi |
High-speed architectures for parallel long BCH encoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 1-6, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BCH, critical loop, iteration bound, parallel processing, encoder, linear feedback shift register, retiming, unfolding, fanout, generator polynomial |
15 | Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001 |
Security Analysis of the Generalized Self-shrinking Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 6th International Conference, ICICS 2004, Malaga, Spain, October 27-29, 2004, Proceedings, pp. 388-400, 2004, Springer, 3-540-23563-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Stream cipher, Linear feedback shift register, Fast correlation attack, Clock control, Self-shrinking generator |
15 | Jason Cong, Yiping Fan, Zhiru Zhang |
Architecture-level synthesis for automatic interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 602-607, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding |
15 | Amihood Amir, Yonatan Aumann, Richard Cole 0001, Moshe Lewenstein, Ely Porat |
Function Matching: Algorithms, Applications, and a Lower Bound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 30th International Colloquium, ICALP 2003, Eindhoven, The Netherlands, June 30 - July 4, 2003. Proceedings, pp. 929-942, 2003, Springer, 3-540-40493-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
function matching, parameterized matching, Pattern matching, register allocation, protein folding, color indexing |
15 | Sandeepan Chowdhury, Subhamoy Maitra |
Efficient Software Implementation of LFSR and Boolean Function and Its Application in Nonlinear Combiner Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACNS ![In: Applied Cryptography and Network Security, First International Conference, ACNS 2003. Kunming, China, October 16-19, 2003, Proceedings, pp. 387-402, 2003, Springer, 3-540-20208-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Block Oriented Software Implementation, Boolean Function, Linear Feedback Shift Register, Resiliency, Nonlinearity, Algebraic Degree |
15 | Achour Mostéfaoui, Sergio Rajsbaum, Michel Raynal, Matthieu Roy |
A Hierarchy of Conditions for Asynchronous Interactive Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 130-140, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Erroneous Value, Fault-Tolerance, Error-Correcting Code, Hamming Distance, Condition, Crash Failure, Atomic Register, Interactive Consistency, Asynchronous Shared Memory System |
15 | Jin Lin, Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan |
A compiler framework for speculative analysis and optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 289-299, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
speculative SSA form, speculative weak update, partial redundancy elimination, data speculation, register promotion |
15 | Toru Akishita, Tsuyoshi Takagi |
Zero-Value Point Attacks on Elliptic Curve Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 6th International Conference, ISC 2003, Bristol, UK, October 1-3, 2003, Proceedings, pp. 218-233, 2003, Springer, 3-540-20176-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
addition formula, zero-value register, side channel attack, differential power analysis, elliptic curve cryptosystem |
15 | Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson |
Reducing translation lookaside buffer active power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 10-13, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
memory management units, low power, register files, translation lookaside buffers, dynamic circuits |
15 | Markus Dichtl |
How to Predict the Output of a Hardware Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings, pp. 181-188, 2003, Springer, 3-540-40833-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Entropy, Linear Feedback Shift Register, Random Number Generator, Cellular Automaton |
15 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 977-994, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing |
15 | Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy |
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 189-201, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scan synthesis, design for testability (DFT), register transfer level (RTL) |
15 | Mayur Naik, Jens Palsberg |
Compiling with code-size constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 120-129, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
banked architecture, register allocation, integer linear programming, space optimization |
15 | Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi |
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 120-125, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure |
15 | Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik |
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 86-91, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
register transfer and gate level descriptions, fault simulation, decision diagrams, Digital systems |
15 | Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt |
Lifetime-Sensitive Modulo Scheduling in a Production Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 234-249, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures |
15 | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg |
Data and memory optimization techniques for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(2), pp. 149-206, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation |
15 | Pei-Chi Wu |
Random number generation with primitive pentanomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Model. Comput. Simul. ![In: ACM Trans. Model. Comput. Simul. 11(4), pp. 346-351, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Primitive trinomials, generalized feedback shift register |
15 | Zhigang Yin, Yinghua Min, Xiaowei Li 0001 |
An Approach to RTL Fault Extraction and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 219-224, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault |
15 | Eric Filiol, Caroline Fontaine |
A New Ultrafast Stream Cipher Design: COS Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMACC ![In: Cryptography and Coding, 8th IMA International Conference, Cirencester, UK, December 17-19, 2001, Proceedings, pp. 85-98, 2001, Springer, 3-540-43026-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
vectorized cipher, high speed encryption, Boolean functions, stream cipher, block cipher, nonlinear feedback shift register |
15 | Chih-Yung Chang, Tzung-Shi Chen, Jang-Ping Sheu |
Improving Memory Traffic by Assembly-Level Exploitation of Reuses for Vector Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 17(2), pp. 187-204, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
vector register, partial reuse, vector compilers, vectorization, data dependence, supercomputer, reuse distance |
15 | Jaan Raik, Raimund Ubar |
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 213-226, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams |
15 | Ashok Sudarsanam, Sharad Malik |
Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(2), pp. 242-264, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
memory bank assignment, code generation, register allocation, code optimization, graph labelling |
15 | Erik Elmroth, Fred G. Gustavson |
High-Performance Library Software for QR Factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing, New Paradigms for HPC in Industry and Academia, 5th International Workshop, PARA 2000 Bergen, Norway, June 18-20, 2000 Proceedings, pp. 53-63, 2000, Springer, 3-540-41729-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Serial and parallel library software, register blocking, unrolling, SMP systems, recursion, dynamic load balancing, QR factorization |
|
|