Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Chun-hong Chen, Chi-Ying Tsui	Towards the capability of providing power-area-delay trade-off at the register transfer level.	ISLPED	1998	DBLP DOI BibTeX RDF
16	Laurence Tianruo Yang, Zebo Peng	An Improved Register-Transfer Level Functional Partitioning Approach for Testability.	EUROMICRO	1998	DBLP DOI BibTeX RDF
16	Randall J. Fisher, Henry G. Dietz	Compiling for SIMD Within a Register.	LCPC	1998	DBLP DOI BibTeX RDF
16	Sandeep Agarwal, Fayez El Guibaly	Modeling of Shift Register-based ATM Switch.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
16	Kazuhito Ito, Keshab K. Parhi	A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
16	Keith D. Cooper, John Lu	Register Promotion in C Programs.	PLDI	1997	DBLP DOI BibTeX RDF	C
16	Catherine H. Gebotys	Low Energy Memory and Register Allocation Using Network Flow.	DAC	1997	DBLP DOI BibTeX RDF
16	Fermín Sánchez, Jordi Cortadella	RESIS: A New Methodology for Register Optimization in Software Pipelining.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
16	Krzysztof Diks, Torben Hagerup	More General Parallel Tree Contraction: Register Allocation and Broadcasting in a Tree.	WG	1996	DBLP DOI BibTeX RDF
16	Johannes Steensma, Francky Catthoor, Hugo De Man	Partial scan and symbolic test at the register-transfer level.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes
16	Chen-Yi Lee, Jer-Min Tsai	A shift register architecture for high-speed data sorting.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
16	Ashok Sudarsanam, Sharad Malik	Memory bank and register allocation in software synthesis for ASIPs.	ICCAD	1995	DBLP DOI BibTeX RDF
16	John A. Nestor	Visual register-transfer description of VLSI microarchitectures.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
16	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
16	Allen C.-H. Wu, Daniel D. Gajski	Partitioning algorithms for layout synthesis from register-transfer netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Miodrag J. Mihaljevic, Jovan Dj. Golic	Convergence of a Bayesian Iterative Error-Correction Procedure on a Noisy Shift register Sequence.	EUROCRYPT	1992	DBLP DOI BibTeX RDF	Algorithms, Cryptanalysis, Convergence, Decoding, Shift registers, Fast correlation attack
16	Michael Merritt, Gadi Taubenfeld	Atomic m-Register Operations (Extended Abstract).	WDAG	1991	DBLP DOI BibTeX RDF
16	Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.	CAV	1990	DBLP DOI BibTeX RDF
16	Gary J. Murakami, Roy H. Campbell, Michael Faiman	Pulsa: Non-Blocking Packet Switching with Shift-Register Rings.	SIGCOMM	1990	DBLP DOI BibTeX RDF
16	Miodrag J. Mihaljevic, Jovan Dj. Golic	A Fast Iterative Algorithm For A Shift Register Initial State Reconstruction Given The Nosiy Output Sequence.	AUSCRYPT	1990	DBLP DOI BibTeX RDF
16	David Callahan, Steve Carr 0001, Ken Kennedy	Improving register allocation for subscripted variables (with retrospective)	Best of PLDI	1990	DBLP DOI BibTeX RDF
16	David Callahan, Steve Carr 0001, Ken Kennedy	Improving Register Allocation for Subscripted Variables.	PLDI	1990	DBLP DOI BibTeX RDF	FORTRAN
16	Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong	Simulation based verification of register-transfer level behavioral synthesis tools.	EURO-DAC	1990	DBLP DOI BibTeX RDF
16	Ranga Vemuri	On the notion of the normal form register-level structures and its applications in design-space exploration.	EURO-DAC	1990	DBLP DOI BibTeX RDF
16	Jovan Dj. Golic, Miodrag J. Mihaljevic	A Noisy Clock-Controlled Shift Register Cryptanalysis Concept Based on Sequence Comparion Approach.	EUROCRYPT	1990	DBLP DOI BibTeX RDF
16	Salvatore Filippone, Paolo Santangelo, Marcello Vitaletti	A vectorized long-period shift-register random number generator.	SC	1990	DBLP DOI BibTeX RDF	FORTRAN
16	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential Test Generation at the Register-Transfer and Logic Levels.	DAC	1990	DBLP DOI BibTeX RDF
16	Preston Briggs, Keith D. Cooper, Ken Kennedy, Linda Torczon	Coloring Heuristics for Register Allocation.	PLDI	1989	DBLP DOI BibTeX RDF	FORTRAN
16	Preston Briggs, Keith D. Cooper, Ken Kennedy, Linda Torczon	Coloring heuristics for register allocation (with retrospective)	Best of PLDI	1989	DBLP DOI BibTeX RDF
16	Réjane Forré	A Fats Correlation Attack on Nonlinearly Feedforward Filtered Shift-Register Sequences.	EUROCRYPT	1989	DBLP DOI BibTeX RDF
16	Gert Goossens, Joos Vandewalle, Hugo De Man	Loop Optimization in Register-Transfer Scheduling for DSP-Systems.	DAC	1989	DBLP DOI BibTeX RDF
16	Fadi J. Kurdahi, Alice C. Parker	REAL: a program for REgister ALlocation.	DAC	1987	DBLP DOI BibTeX RDF
16	James R. Larus, Paul N. Hilfinger	Register allocation in the SPUR Lisp compiler.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF	LISP, LISP
16	Harald Niederreiter	A Public-Key Cryptosystem based on Shift Register Sequences.	EUROCRYPT	1985	DBLP DOI BibTeX RDF
16	Tore Herlestam	On Functions of Linear Shift Register Sequences.	EUROCRYPT	1985	DBLP DOI BibTeX RDF
16	Ted G. Lewis, William H. Payne	Generalized Feedback Shift Register Pseudorandom Number Algorithm.	J. ACM	1973	DBLP DOI BibTeX RDF
16	Lawrence Paul Horwitz, Richard M. Karp, Raymond E. Miller, Shmuel Winograd	Index Register Allocation.	J. ACM	1966	DBLP DOI BibTeX RDF
15	Amit Golander, Shlomo Weiss	Checkpoint allocation and release.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback
15	Sandrine Blazy, Benoît Robillard	Live-range unsplitting for faster optimal coalescing.	LCTES	2009	DBLP DOI BibTeX RDF	register allocation, graph reduction, coalescing
15	Andreas Larsson, Anders Gidenstam, Phuong Hoai Ha, Marina Papatriantafilou, Philippas Tsigas	Multiword atomic read/write registers on multiprocessor systems.	ACM J. Exp. Algorithmics	2008	DBLP DOI BibTeX RDF	synchronization, wait-free, Atomic register
15	Thomas Kotzmann, Christian Wimmer, Hanspeter Mössenböck, Thomas Rodriguez, Kenneth B. Russell, David Cox	Design of the Java HotSpot™ client compiler for Java 6.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	deoptimization, Java, optimization, compiler, register allocation, just-in-time compilation, intermediate representation
15	Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
15	Xuejun Yang, Ying Zhang 0032, Jingling Xue, Ian Rogers, Gen Li 0002, Guibin Wang	Exploiting loop-dependent stream reuse for stream processors.	PACT	2008	DBLP DOI BibTeX RDF	StreamC, stream professor, stream register file, stream reuse, stream programming model
15	Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi	Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing
15	Ricky Yiu-kee Choi, Chi-Ying Tsui	A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.	ISQED	2008	DBLP DOI BibTeX RDF	Successive Approximation Register ADC, Low Power
15	Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham	Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit
15	Mathias Ortner, Xavier Descombes, Josiane Zerubia	Building Outline Extraction from Digital Elevation Models Using Marked Point Processes.	Int. J. Comput. Vis.	2007	DBLP DOI BibTeX RDF	inhomogeneous Poisson point process, dense urban area, laser data, land register, RJMCMC, image processing, simulated annealing, MCMC, stochastic geometry, digital elevation models, building detection
15	Daniel J. Bernstein, Tanja Lange 0001	Faster Addition and Doubling on Elliptic Curves.	ASIACRYPT	2007	DBLP DOI BibTeX RDF	multi-scalar multiplication, side-channel countermeasures, unified addition formulas, complete addition formulas, performance evaluation, Elliptic curves, register allocation, scalar multiplication, efficient implementation, addition, explicit formulas, doubling
15	Weijia Li, Youtao Zhang, Jun Yang 0002, Jiang Zheng 0002	UCC: update-conscious compilation for energy efficiency in wireless sensor networks.	PLDI	2007	DBLP DOI BibTeX RDF	sensor networks, register allocation, code dissemination
15	Soheil Aminzadeh, Saeed Safari	Co-evolutionary high-level test synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	co-evolutionary algorithm, module binding, genetic algorithm, scheduling, register allocation, high-level test synthesis
15	Joel David Hamkins, David Linetsky, Russell G. Miller	The Complexity of Quickly ORM-Decidable Sets.	CiE	2007	DBLP DOI BibTeX RDF	ordinal computation, infinite time computation, hyperarithmetical hierarchy, complexity, computability, Ordinal, arithmetical hierarchy, register machine
15	Alex Gontmakher, Avi Mendelson, Assaf Schuster	Using fine grain multithreading for energy efficient computing.	PPoPP	2007	DBLP DOI BibTeX RDF	register sharing, energy efficiency, fine grain parallelization
15	Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope	Supporting Microthread Scheduling and Synchronisation in CMPs.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Microgrids, microthreads, schedulers, CMPs, register files
15	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Offset assignment using simultaneous variable coalescing.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
15	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
15	George Petrides, Johannes Mykkeltveit	On the Classification of Periodic Binary Sequences into Nonlinear Complexity Classes.	SETA	2006	DBLP DOI BibTeX RDF	Nonlinear complexity, short cycles, nonlinear feedback shift register
15	Bin Zhang 0003, Dengguo Feng	New Guess-and-Determine Attack on the Self-Shrinking Generator.	ASIACRYPT	2006	DBLP DOI BibTeX RDF	Self-shrinking, Guess-and-determine, Stream cipher, Linear feedback shift register (LFSR)
15	Dongwon Jeong, Youn-Hee Han	Resolving the Semantic Inconsistency Problem for Ubiquitous RFID Applications.	UIC	2006	DBLP DOI BibTeX RDF	Metadata register, Ubiquitous computing, Semantic, Interoperability, RFID, Consistency
15	Michel Raynal, Corentin Travers	In Search of the Holy Grail: Looking for the Weakest Failure Detector for Wait-Free Set Agreement.	OPODIS	2006	DBLP DOI BibTeX RDF	Leader oracle, Participating process, Consensus, Asynchronous system, Shared object, Atomic register, Set agreement, Asynchronous algorithm, Wait-free algorithm
15	Yi-Bing Lin	Per-User Checkpointing for Mobility Database Failure Restoration.	IEEE Trans. Mob. Comput.	2005	DBLP DOI BibTeX RDF	failure restoration, Checkpoint, Universal Mobile Telecommunications System (UMTS), General Packet Radio Service (GPRS), Home Location Register
15	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
15	François Panneton, Pierre L'Ecuyer	On the xorshift random number generators.	ACM Trans. Model. Comput. Simul.	2005	DBLP DOI BibTeX RDF	linear recurrence modulo 2, xorshift, linear feedback shift register, Random number generation
15	Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang	Instruction set extension with shadow registers for configurable processors.	FPGA	2005	DBLP DOI BibTeX RDF	shadow register, compilation, ASIP, configurable processor
15	Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Hong Wang	Weaknesses of COSvd (2, 128) Stream Cipher.	ICISC	2005	DBLP DOI BibTeX RDF	COS cipher, Non- linear feedback shift register, Stream cipher, Divide-and-Conquer
15	Hyun-Gyu Kim, Hyeong-Cheol Oh	A DSP-Enhanced 32-Bit Embedded Microprocessor.	EUC	2005	DBLP DOI BibTeX RDF	DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD
15	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
15	Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001	A Fast Correlation Attack on the Shrinking Generator.	CT-RSA	2005	DBLP DOI BibTeX RDF	Linear feedback shift register, Fast correlation attack, Shrinking generator
15	Bogdan S. Chlebus, Dariusz R. Kowalski	Cooperative asynchronous update of shared memory.	STOC	2005	DBLP DOI BibTeX RDF	problem Write-All, read and write register, work efficiency, distributed algorithm, expander, asynchrony, disperser
15	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
15	Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov	Architecture-aware classical Taylor shift by 1.	ISSAC	2005	DBLP DOI BibTeX RDF	ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling
15	Dmitri Bronnikov	A practical adoption of partial redundancy elimination.	ACM SIGPLAN Notices	2004	DBLP DOI BibTeX RDF	partial redundancy elimination, register spilling
15	Jin Lin, Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan	A compiler framework for speculative optimizations.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	speculative SSA form, speculative weak update, partial redundancy elimination, Data speculation, register promotion
15	Mayur Naik, Jens Palsberg	Compiling with code-size constraints.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Banked architecture, register allocation, integer linear programming, space optimization
15	Kellie Michele Evans	Is Bosco's Rule Universal?	MCU	2004	DBLP DOI BibTeX RDF	gliders, Larger than Life, sliding block memory, spaceships, cellular automata, universal, bugs, register, Game of Life
15	Carole Delporte-Gallet, Hugues Fauconnier, Rachid Guerraoui, Vassos Hadzilacos, Petr Kouznetsov, Sam Toueg	The weakest failure detectors to solve certain fundamental problems in distributed computing.	PODC	2004	DBLP DOI BibTeX RDF	non-blocking atomic commit, quittable consensus, weakest failure detector, consensus, register
15	Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001	Chosen Ciphertext Attack on a New Class of Self-Synchronizing Stream Ciphers.	INDOCRYPT	2004	DBLP DOI BibTeX RDF	2-adic expansion, Stream cipher, Self-synchronizing, Feedback shift register
15	Xinmiao Zhang, Keshab K. Parhi	High-speed architectures for parallel long BCH encoders.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BCH, critical loop, iteration bound, parallel processing, encoder, linear feedback shift register, retiming, unfolding, fanout, generator polynomial
15	Bin Zhang 0003, Hongjun Wu 0001, Dengguo Feng, Feng Bao 0001	Security Analysis of the Generalized Self-shrinking Generator.	ICICS	2004	DBLP DOI BibTeX RDF	Stream cipher, Linear feedback shift register, Fast correlation attack, Clock control, Self-shrinking generator
15	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
15	Amihood Amir, Yonatan Aumann, Richard Cole 0001, Moshe Lewenstein, Ely Porat	Function Matching: Algorithms, Applications, and a Lower Bound.	ICALP	2003	DBLP DOI BibTeX RDF	function matching, parameterized matching, Pattern matching, register allocation, protein folding, color indexing
15	Sandeepan Chowdhury, Subhamoy Maitra	Efficient Software Implementation of LFSR and Boolean Function and Its Application in Nonlinear Combiner Model.	ACNS	2003	DBLP DOI BibTeX RDF	Block Oriented Software Implementation, Boolean Function, Linear Feedback Shift Register, Resiliency, Nonlinearity, Algebraic Degree
15	Achour Mostéfaoui, Sergio Rajsbaum, Michel Raynal, Matthieu Roy	A Hierarchy of Conditions for Asynchronous Interactive Consistency.	PaCT	2003	DBLP DOI BibTeX RDF	Erroneous Value, Fault-Tolerance, Error-Correcting Code, Hamming Distance, Condition, Crash Failure, Atomic Register, Interactive Consistency, Asynchronous Shared Memory System
15	Jin Lin, Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan	A compiler framework for speculative analysis and optimizations.	PLDI	2003	DBLP DOI BibTeX RDF	speculative SSA form, speculative weak update, partial redundancy elimination, data speculation, register promotion
15	Toru Akishita, Tsuyoshi Takagi	Zero-Value Point Attacks on Elliptic Curve Cryptosystem.	ISC	2003	DBLP DOI BibTeX RDF	addition formula, zero-value register, side channel attack, differential power analysis, elliptic curve cryptosystem
15	Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson	Reducing translation lookaside buffer active power.	ISLPED	2003	DBLP DOI BibTeX RDF	memory management units, low power, register files, translation lookaside buffers, dynamic circuits
15	Markus Dichtl	How to Predict the Output of a Hardware Random Number Generator.	CHES	2003	DBLP DOI BibTeX RDF	Entropy, Linear Feedback Shift Register, Random Number Generator, Cellular Automaton
15	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
15	Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy	Synthesis of Scan Chains for Netlist Descriptions at RT-Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	scan synthesis, design for testability (DFT), register transfer level (RTL)
15	Mayur Naik, Jens Palsberg	Compiling with code-size constraints.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	banked architecture, register allocation, integer linear programming, space optimization
15	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .	ISSS	2002	DBLP DOI BibTeX RDF	compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure
15	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.	DELTA	2002	DBLP DOI BibTeX RDF	register transfer and gate level descriptions, fault simulation, decision diagrams, Digital systems
15	Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
15	Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg	Data and memory optimization techniques for embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation
15	Pei-Chi Wu	Random number generation with primitive pentanomials.	ACM Trans. Model. Comput. Simul.	2001	DBLP DOI BibTeX RDF	Primitive trinomials, generalized feedback shift register
15	Zhigang Yin, Yinghua Min, Xiaowei Li 0001	An Approach to RTL Fault Extraction and Test Generation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault
15	Eric Filiol, Caroline Fontaine	A New Ultrafast Stream Cipher Design: COS Ciphers.	IMACC	2001	DBLP DOI BibTeX RDF	vectorized cipher, high speed encryption, Boolean functions, stream cipher, block cipher, nonlinear feedback shift register
15	Chih-Yung Chang, Tzung-Shi Chen, Jang-Ping Sheu	Improving Memory Traffic by Assembly-Level Exploitation of Reuses for Vector Registers.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	vector register, partial reuse, vector compilers, vectorization, data dependence, supercomputer, reuse distance
15	Jaan Raik, Raimund Ubar	Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams
15	Ashok Sudarsanam, Sharad Malik	Simultaneous reference allocation in code generation for dual data memory bank ASIPs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	memory bank assignment, code generation, register allocation, code optimization, graph labelling
15	Erik Elmroth, Fred G. Gustavson	High-Performance Library Software for QR Factorization.	PARA	2000	DBLP DOI BibTeX RDF	Serial and parallel library software, register blocking, unrolling, SMP systems, recursion, dynamic load balancing, QR factorization