Search results for "ASAP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Jérémie Detrey, Florent de Dinechin	Table-based polynomials for fast hardware function evaluation.	ASAP	2005	DBLP DOI BibTeX RDF
34	Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	A. Murat Fiskiran, Ruby B. Lee	On-Chip Lookup Tables for Fast Symmetric-Key Encryption.	ASAP	2005	DBLP DOI BibTeX RDF
34	Ümit Y. Ogras, Jingcao Hu, Radu Marculescu	Communication-Centric SoC Design for Nanoscale Domain.	ASAP	2005	DBLP DOI BibTeX RDF
34	Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta	Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors.	ASAP	2005	DBLP DOI BibTeX RDF
34	Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio 0001	CONAN - A Design Exploration Framework for Reliable Nano-Electronics.	ASAP	2005	DBLP DOI BibTeX RDF
34	Byeong Kil Lee, Lizy Kurian John, Eugene John	Architectural Support for Accelerating Congestion Control Applications in Network Processors.	ASAP	2005	DBLP DOI BibTeX RDF
34		15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA	ASAP	2004	DBLP BibTeX RDF
34	Johann Großschädl, Sandeep S. Kumar, Christof Paar	Architectural Support for Arithmetic in Optimal Extension Fields.	ASAP	2004	DBLP DOI BibTeX RDF
34	Valeriu Beiu	A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.	ASAP	2004	DBLP DOI BibTeX RDF
34	Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni	Hyper-Programmable Architectures for Adaptable Networked Systems.	ASAP	2004	DBLP DOI BibTeX RDF
34	François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner	Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations.	ASAP	2004	DBLP DOI BibTeX RDF	multi-rate systems, systems of recurrence equations, data flow systems, 3G mobile telephony, scheduling, FPGA, prototyping, WCDMA
34	Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala	Stride Permutation Networks for Array Processors.	ASAP	2004	DBLP DOI BibTeX RDF
34	Antoine Fraboulet, Tanguy Risset	Efficient On-Chip Communications for Data-Flow IPs.	ASAP	2004	DBLP DOI BibTeX RDF	SoC simulation, system on chip, High level synthesis, interface generation
34	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.	ASAP	2004	DBLP DOI BibTeX RDF
34	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis.	ASAP	2004	DBLP DOI BibTeX RDF
34	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
34	Oliver Amft, Michael Lauffer, Stijn Ossevoort, Fabrizio Macaluso, Paul Lukowicz, Gerhard Tröster	Design of the QBIC Wearable Computing Platform.	ASAP	2004	DBLP DOI BibTeX RDF
34	Tom Van Court, Martin C. Herbordt	Families of FPGA-Based Algorithms for Approximate String Matching.	ASAP	2004	DBLP DOI BibTeX RDF
34	Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke	Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.	ASAP	2004	DBLP DOI BibTeX RDF
34	Fabien Castanier, Alberto Ferrante, Vincenzo Piuri	A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems.	ASAP	2004	DBLP DOI BibTeX RDF
34	Rama Sangireddy	Register Organization for Enhanced On-Chip Parallelism.	ASAP	2004	DBLP DOI BibTeX RDF
34	Alexandre F. Tenca, Ajay C. Shantilal, Mohammed H. Sinky	Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
34	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao 0001, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
34	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	Binary Multiplication based on Single Electron Tunneling.	ASAP	2004	DBLP DOI BibTeX RDF
34	Luca Breveglieri, Israel Koren, Paolo Maistri	Detecting Faults in Four Symmetric Key Block Ciphers.	ASAP	2004	DBLP DOI BibTeX RDF
34	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Division Using Newton-Raphson Iteration.	ASAP	2004	DBLP DOI BibTeX RDF
34	Vida Kianzad, Shuvra S. Bhattacharyya	CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems.	ASAP	2004	DBLP DOI BibTeX RDF
34	Jongmyon Kim, D. Scott Wills	Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems.	ASAP	2004	DBLP DOI BibTeX RDF
34	Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram	A Public-Key Cryptographic Processor for RSA and ECC.	ASAP	2004	DBLP DOI BibTeX RDF
34	Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase	Parallel Montgomery Multipliers.	ASAP	2004	DBLP DOI BibTeX RDF
34	Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster	Biosequence Similarity Search on the Mercury System.	ASAP	2004	DBLP DOI BibTeX RDF
34	Sebastian Siegel, Renate Merker	Optimized Data-Reuse in Processor Arrays.	ASAP	2004	DBLP DOI BibTeX RDF
34	Yuan Xie 0001, Lin Li 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reliability-Aware Co-Synthesis for Embedded Systems.	ASAP	2004	DBLP DOI BibTeX RDF
34	Milos D. Ercegovac, Jean-Michel Muller	Complex Square Root with Operand Prescaling.	ASAP	2004	DBLP DOI BibTeX RDF
34	Alex Fit-Florea, David W. Matula	A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.	ASAP	2004	DBLP DOI BibTeX RDF
34	Lo'ai Ali Tawalbeh, Alexandre F. Tenca	An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2n).	ASAP	2004	DBLP DOI BibTeX RDF
34	A. Murat Fiskiran, Ruby B. Lee	Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields.	ASAP	2004	DBLP DOI BibTeX RDF
34	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks.	ASAP	2004	DBLP DOI BibTeX RDF
34	Frank Hannig, Jürgen Teich	Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.	ASAP	2004	DBLP DOI BibTeX RDF
34	Ljiljana Dilparic, D. K. Arvind 0001	Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices.	ASAP	2004	DBLP DOI BibTeX RDF
34	José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor	Optimizing the Memory Bandwidth with Loop Morphing.	ASAP	2004	DBLP DOI BibTeX RDF
34	Ruby B. Lee	Challenges in the Design of Security-Aware Processors.	ASAP	2003	DBLP DOI BibTeX RDF
34	Rama Sangireddy, Arun K. Somani	Application-Specific Computing with Adaptive Register File Architectures.	ASAP	2003	DBLP DOI BibTeX RDF	Computing capacity, compute-intensive Function, Memory bandwidth, Register File
34	Johann Großschädl, Guy-Armand Kamendje	Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m).	ASAP	2003	DBLP DOI BibTeX RDF
34	Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, Girish Venkataramani	Reconfigurable Computing and Electronic Nanotechnology.	ASAP	2003	DBLP DOI BibTeX RDF
34	Swee Yeow Yap, John V. McCanny	A VLSI Architecture for Advanced Video Coding Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
34	Hans Eberle, Nils Gura, Sheueling Chang Shantz	A Cryptograhpic Processor for Arbitrary Elliptic Curves over.	ASAP	2003	DBLP DOI BibTeX RDF
34	Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli	Automatic Instruction Set Extension and Utilization for Embedded Processors.	ASAP	2003	DBLP DOI BibTeX RDF
34	Zhijie Shi, Xiao Yang 0001, Ruby B. Lee	Arbitrary Bit Permutations in One or Two Cycles.	ASAP	2003	DBLP DOI BibTeX RDF
34	Alexandru Turjan, Bart Kienhuis	Storage Management in Process Networks using the Lexicographically Maximal Preimage.	ASAP	2003	DBLP DOI BibTeX RDF
34	Chichyang Chen, Rui-Lin Chen	Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic.	ASAP	2003	DBLP DOI BibTeX RDF
34	Thorsten Dräger, Gerhard P. Fettweis	Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs.	ASAP	2003	DBLP DOI BibTeX RDF
34	Yiqun Zhu, Mohammed Benaissa	Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique.	ASAP	2003	DBLP DOI BibTeX RDF
34	Ayman M. El-Khashab, Earl E. Swartzlander Jr.	An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
34	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven	Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.	ASAP	2003	DBLP DOI BibTeX RDF
34	José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez	Energy Aware Register File Implementation through Instruction Predecode.	ASAP	2003	DBLP DOI BibTeX RDF
34	Jung-Yup Kang, Sandeep Gupta 0001, Saurabh Shah, Jean-Luc Gaudiot	An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
34	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
34	Sven Verdoolaege, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor	Multi-dimentsional Incremetal Loops Fusion for Data Locality.	ASAP	2003	DBLP DOI BibTeX RDF
34	George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou	GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks.	ASAP	2003	DBLP DOI BibTeX RDF
34	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
34	Zhaohui Liu, Kevin Dickson, John V. McCanny	A floating-point CORDIC based SVD processor.	ASAP	2003	DBLP DOI BibTeX RDF
34	Terry Tao Ye, Giovanni De Micheli	Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.	ASAP	2003	DBLP DOI BibTeX RDF
34	Piia Simonen, Ilkka Saastamoinen, Jari Nurmi	Variable-Length Instruction Compression for Area Minimization.	ASAP	2003	DBLP DOI BibTeX RDF
34	Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner	Combined Multiplication and Sum-of-Squares Units.	ASAP	2003	DBLP DOI BibTeX RDF
34	James Irwin, Dan Page	Using Media Processors for Low-Memory AES Implementation.	ASAP	2003	DBLP DOI BibTeX RDF
34	Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro	Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers.	ASAP	2003	DBLP DOI BibTeX RDF
34	Anne-Claire Guillou, Patrice Quinton, Tanguy Risset	Hardware Synthesis for Multi-Dimensional Time.	ASAP	2003	DBLP DOI BibTeX RDF	multi-dimensional scheduling, fpga, High-level synthesis, systolic architecture
34	Jean-Michel Muller	Complex Division with Prescaling of Operands.	ASAP	2003	DBLP DOI BibTeX RDF
34	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
34	Lai-Sze Au, Neil Burgess	Unified Radix-4 Multiplier for GF(p) and GF(2^n).	ASAP	2003	DBLP DOI BibTeX RDF
34	Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle	Hardware Implementation of an Elliptic Curve Processor over GF(p).	ASAP	2003	DBLP DOI BibTeX RDF	Modular Operations, FPGA, Elliptic Curve Cryptosystems
34	Mark G. Arnold	Iterative Methods for Logarithmic Subtraction.	ASAP	2003	DBLP DOI BibTeX RDF
34	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.	ASAP	2003	DBLP DOI BibTeX RDF
34	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
34	Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann 0002	Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization.	ASAP	2003	DBLP DOI BibTeX RDF
34	Abhishek Singh 0001, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel	Comparison of Branching CORDIC Implementations.	ASAP	2003	DBLP DOI BibTeX RDF
34	Jean-Luc Beuchat	Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.	ASAP	2003	DBLP DOI BibTeX RDF
34	Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye	Switched Memory Architectures-Moving Beyond Systolic Arrays.	ASAP	2003	DBLP DOI BibTeX RDF
34	P. H. Chan, Jack Y. B. Lee	An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System.	ASAP	2003	DBLP DOI BibTeX RDF
34	Toshishige Yamada, M. Meyyappan	Nanotechnology in the Development of Future Computing Systems.	ASAP	2003	DBLP DOI BibTeX RDF
34	Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere	Context-Aware Process Networks.	ASAP	2003	DBLP DOI BibTeX RDF
34	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.	ASAP	2003	DBLP DOI BibTeX RDF
34	Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo	Application-Specific DSP Architecture For Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
34	David B. Janes, Subhasis Ghosh, Jaewon Choi, Saurabh Lodha	Circuit Characteristics of Molecular Electronic Components.	ASAP	2003	DBLP DOI BibTeX RDF
34	Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima	A Component Architecture for FPGA-Based, DSP System Design.	ASAP	2002	DBLP DOI BibTeX RDF
34	Alain Darte, Guillaume Huard	New Results on Array Contraction.	ASAP	2002	DBLP DOI BibTeX RDF
34	Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang	A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.	ASAP	2002	DBLP DOI BibTeX RDF
34	David Cachera, Tanguy Risset	Advances in Bit Width Selection Methodology.	ASAP	2002	DBLP DOI BibTeX RDF
34	Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata	Polynomial Evaluation on Multimedia Processors.	ASAP	2002	DBLP DOI BibTeX RDF
34	Ahmet Akkas	A Combined Interval and Floating-Point Comparator/Selector.	ASAP	2002	DBLP DOI BibTeX RDF	VLSI design, Interval arithmetic, floating-point arithmetic, comparator, specialized hardware, selector
34	Chih-Chung Lu, Shau-Yin Tseng	Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter.	ASAP	2002	DBLP DOI BibTeX RDF
34	Wen-Tsong Shiue	Low Power Memory Design.	ASAP	2002	DBLP DOI BibTeX RDF
34	James Irwin, David May 0001, Henk L. Muller, Dan Page	Predictable Instruction Caching for Media Processors.	ASAP	2002	DBLP DOI BibTeX RDF
34	Byeong Kil Lee, Lizy Kurian John	Implications of Programmable General Purpose Processors for Compression/Encryption Applications.	ASAP	2002	DBLP DOI BibTeX RDF
34	Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin	Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System.	ASAP	2002	DBLP DOI BibTeX RDF
34	Mehboob Alam, Wael M. Badawy, Graham A. Jullien	A Novel Pipelined Threads Architecture for AES Encryption Algorithm.	ASAP	2002	DBLP DOI BibTeX RDF
34	K. Sitaraman, N. Ranganathan, Abdel Ejnioui	A VLSI Architecture for Object Recognition Using Tree Matching.	ASAP	2002	DBLP DOI BibTeX RDF
34	José A. B. Fortes	Nanocomputing with Delays.	ASAP	2002	DBLP DOI BibTeX RDF