Search results for "ASAP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Alexandre F. Tenca, Ajay C. Shantilal, Mohammed H. Sinky	Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao 0001, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
1	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	Binary Multiplication based on Single Electron Tunneling.	ASAP	2004	DBLP DOI BibTeX RDF
1	Luca Breveglieri, Israel Koren, Paolo Maistri	Detecting Faults in Four Symmetric Key Block Ciphers.	ASAP	2004	DBLP DOI BibTeX RDF
1	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Division Using Newton-Raphson Iteration.	ASAP	2004	DBLP DOI BibTeX RDF
1	Vida Kianzad, Shuvra S. Bhattacharyya	CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems.	ASAP	2004	DBLP DOI BibTeX RDF
1	Jongmyon Kim, D. Scott Wills	Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems.	ASAP	2004	DBLP DOI BibTeX RDF
1	Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram	A Public-Key Cryptographic Processor for RSA and ECC.	ASAP	2004	DBLP DOI BibTeX RDF
1	Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase	Parallel Montgomery Multipliers.	ASAP	2004	DBLP DOI BibTeX RDF
1	Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster	Biosequence Similarity Search on the Mercury System.	ASAP	2004	DBLP DOI BibTeX RDF
1	Sebastian Siegel, Renate Merker	Optimized Data-Reuse in Processor Arrays.	ASAP	2004	DBLP DOI BibTeX RDF
1	Yuan Xie 0001, Lin Li 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reliability-Aware Co-Synthesis for Embedded Systems.	ASAP	2004	DBLP DOI BibTeX RDF
1	Milos D. Ercegovac, Jean-Michel Muller	Complex Square Root with Operand Prescaling.	ASAP	2004	DBLP DOI BibTeX RDF
1	Alex Fit-Florea, David W. Matula	A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.	ASAP	2004	DBLP DOI BibTeX RDF
1	Lo'ai Ali Tawalbeh, Alexandre F. Tenca	An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2n).	ASAP	2004	DBLP DOI BibTeX RDF
1	A. Murat Fiskiran, Ruby B. Lee	Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields.	ASAP	2004	DBLP DOI BibTeX RDF
1	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks.	ASAP	2004	DBLP DOI BibTeX RDF
1	Frank Hannig, Jürgen Teich	Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.	ASAP	2004	DBLP DOI BibTeX RDF
1	Ljiljana Dilparic, D. K. Arvind 0001	Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices.	ASAP	2004	DBLP DOI BibTeX RDF
1	José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor	Optimizing the Memory Bandwidth with Loop Morphing.	ASAP	2004	DBLP DOI BibTeX RDF
1	Ruby B. Lee	Challenges in the Design of Security-Aware Processors.	ASAP	2003	DBLP DOI BibTeX RDF
1	Rama Sangireddy, Arun K. Somani	Application-Specific Computing with Adaptive Register File Architectures.	ASAP	2003	DBLP DOI BibTeX RDF	Computing capacity, compute-intensive Function, Memory bandwidth, Register File
1	Johann Großschädl, Guy-Armand Kamendje	Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m).	ASAP	2003	DBLP DOI BibTeX RDF
1	Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, Girish Venkataramani	Reconfigurable Computing and Electronic Nanotechnology.	ASAP	2003	DBLP DOI BibTeX RDF
1	Swee Yeow Yap, John V. McCanny	A VLSI Architecture for Advanced Video Coding Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
1	Hans Eberle, Nils Gura, Sheueling Chang Shantz	A Cryptograhpic Processor for Arbitrary Elliptic Curves over.	ASAP	2003	DBLP DOI BibTeX RDF
1	Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli	Automatic Instruction Set Extension and Utilization for Embedded Processors.	ASAP	2003	DBLP DOI BibTeX RDF
1	Zhijie Shi, Xiao Yang 0001, Ruby B. Lee	Arbitrary Bit Permutations in One or Two Cycles.	ASAP	2003	DBLP DOI BibTeX RDF
1	Alexandru Turjan, Bart Kienhuis	Storage Management in Process Networks using the Lexicographically Maximal Preimage.	ASAP	2003	DBLP DOI BibTeX RDF
1	Chichyang Chen, Rui-Lin Chen	Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic.	ASAP	2003	DBLP DOI BibTeX RDF
1	Thorsten Dräger, Gerhard P. Fettweis	Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs.	ASAP	2003	DBLP DOI BibTeX RDF
1	Yiqun Zhu, Mohammed Benaissa	Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique.	ASAP	2003	DBLP DOI BibTeX RDF
1	Ayman M. El-Khashab, Earl E. Swartzlander Jr.	An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
1	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven	Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.	ASAP	2003	DBLP DOI BibTeX RDF
1	José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez	Energy Aware Register File Implementation through Instruction Predecode.	ASAP	2003	DBLP DOI BibTeX RDF
1	Jung-Yup Kang, Sandeep Gupta 0001, Saurabh Shah, Jean-Luc Gaudiot	An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
1	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
1	Sven Verdoolaege, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor	Multi-dimentsional Incremetal Loops Fusion for Data Locality.	ASAP	2003	DBLP DOI BibTeX RDF
1	George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou	GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks.	ASAP	2003	DBLP DOI BibTeX RDF
1	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
1	Zhaohui Liu, Kevin Dickson, John V. McCanny	A floating-point CORDIC based SVD processor.	ASAP	2003	DBLP DOI BibTeX RDF
1	Terry Tao Ye, Giovanni De Micheli	Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.	ASAP	2003	DBLP DOI BibTeX RDF
1	Piia Simonen, Ilkka Saastamoinen, Jari Nurmi	Variable-Length Instruction Compression for Area Minimization.	ASAP	2003	DBLP DOI BibTeX RDF
1	Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner	Combined Multiplication and Sum-of-Squares Units.	ASAP	2003	DBLP DOI BibTeX RDF
1	James Irwin, Dan Page	Using Media Processors for Low-Memory AES Implementation.	ASAP	2003	DBLP DOI BibTeX RDF
1	Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro	Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers.	ASAP	2003	DBLP DOI BibTeX RDF
1	Anne-Claire Guillou, Patrice Quinton, Tanguy Risset	Hardware Synthesis for Multi-Dimensional Time.	ASAP	2003	DBLP DOI BibTeX RDF	multi-dimensional scheduling, fpga, High-level synthesis, systolic architecture
1	Jean-Michel Muller	Complex Division with Prescaling of Operands.	ASAP	2003	DBLP DOI BibTeX RDF
1	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
1	Lai-Sze Au, Neil Burgess	Unified Radix-4 Multiplier for GF(p) and GF(2^n).	ASAP	2003	DBLP DOI BibTeX RDF
1	Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle	Hardware Implementation of an Elliptic Curve Processor over GF(p).	ASAP	2003	DBLP DOI BibTeX RDF	Modular Operations, FPGA, Elliptic Curve Cryptosystems
1	Mark G. Arnold	Iterative Methods for Logarithmic Subtraction.	ASAP	2003	DBLP DOI BibTeX RDF
1	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.	ASAP	2003	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
1	Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann 0002	Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization.	ASAP	2003	DBLP DOI BibTeX RDF
1	Abhishek Singh 0001, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel	Comparison of Branching CORDIC Implementations.	ASAP	2003	DBLP DOI BibTeX RDF
1	Jean-Luc Beuchat	Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.	ASAP	2003	DBLP DOI BibTeX RDF
1	Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye	Switched Memory Architectures-Moving Beyond Systolic Arrays.	ASAP	2003	DBLP DOI BibTeX RDF
1	P. H. Chan, Jack Y. B. Lee	An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System.	ASAP	2003	DBLP DOI BibTeX RDF
1	Toshishige Yamada, M. Meyyappan	Nanotechnology in the Development of Future Computing Systems.	ASAP	2003	DBLP DOI BibTeX RDF
1	Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere	Context-Aware Process Networks.	ASAP	2003	DBLP DOI BibTeX RDF
1	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.	ASAP	2003	DBLP DOI BibTeX RDF
1	Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo	Application-Specific DSP Architecture For Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
1	David B. Janes, Subhasis Ghosh, Jaewon Choi, Saurabh Lodha	Circuit Characteristics of Molecular Electronic Components.	ASAP	2003	DBLP DOI BibTeX RDF
1	Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima	A Component Architecture for FPGA-Based, DSP System Design.	ASAP	2002	DBLP DOI BibTeX RDF
1	Alain Darte, Guillaume Huard	New Results on Array Contraction.	ASAP	2002	DBLP DOI BibTeX RDF
1	Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang	A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.	ASAP	2002	DBLP DOI BibTeX RDF
1	David Cachera, Tanguy Risset	Advances in Bit Width Selection Methodology.	ASAP	2002	DBLP DOI BibTeX RDF
1	Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata	Polynomial Evaluation on Multimedia Processors.	ASAP	2002	DBLP DOI BibTeX RDF
1	Ahmet Akkas	A Combined Interval and Floating-Point Comparator/Selector.	ASAP	2002	DBLP DOI BibTeX RDF	VLSI design, Interval arithmetic, floating-point arithmetic, comparator, specialized hardware, selector
1	Chih-Chung Lu, Shau-Yin Tseng	Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter.	ASAP	2002	DBLP DOI BibTeX RDF
1	Wen-Tsong Shiue	Low Power Memory Design.	ASAP	2002	DBLP DOI BibTeX RDF
1	James Irwin, David May 0001, Henk L. Muller, Dan Page	Predictable Instruction Caching for Media Processors.	ASAP	2002	DBLP DOI BibTeX RDF
1	Byeong Kil Lee, Lizy Kurian John	Implications of Programmable General Purpose Processors for Compression/Encryption Applications.	ASAP	2002	DBLP DOI BibTeX RDF
1	Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin	Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System.	ASAP	2002	DBLP DOI BibTeX RDF
1	Mehboob Alam, Wael M. Badawy, Graham A. Jullien	A Novel Pipelined Threads Architecture for AES Encryption Algorithm.	ASAP	2002	DBLP DOI BibTeX RDF
1	K. Sitaraman, N. Ranganathan, Abdel Ejnioui	A VLSI Architecture for Object Recognition Using Tree Matching.	ASAP	2002	DBLP DOI BibTeX RDF
1	José A. B. Fortes	Nanocomputing with Delays.	ASAP	2002	DBLP DOI BibTeX RDF
1	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
1	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	High-Radix Logarithm with Selection by Rounding.	ASAP	2002	DBLP DOI BibTeX RDF
1	Mark G. Arnold	Reduced Power Consumption for MPEG Decoding with LNS.	ASAP	2002	DBLP DOI BibTeX RDF	Low Power Design, Discrete Cosine Transform(DCT), Computer Arithmetic, MPEG, multi-media, Logarithmic Number Systems (LNS)
1	Chris Y. Chung, Ravi Managuli, Yongmin Kim 0001	Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline.	ASAP	2002	DBLP DOI BibTeX RDF
1	Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang 0001	Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments.	ASAP	2002	DBLP DOI BibTeX RDF
1	Tsai-Yun Liao, Ta-Yin Hu	A CORBA-Based GIS-T for Ambulance Assignment.	ASAP	2002	DBLP DOI BibTeX RDF
1	Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim	Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.	ASAP	2002	DBLP DOI BibTeX RDF
1	E. I. Chester, John N. Coleman	Matrix Engine for Signal Processing Applications Using the Logarithmic Number System.	ASAP	2002	DBLP DOI BibTeX RDF
1	James Irwin, Dan Page, Nigel P. Smart	Instruction Stream Mutation for Non-Deterministic Processors.	ASAP	2002	DBLP DOI BibTeX RDF
1	Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy	Optical Network Reconfiguration for Signal Processing Applications.	ASAP	2002	DBLP DOI BibTeX RDF
1	Neil Burgess	PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications.	ASAP	2002	DBLP DOI BibTeX RDF
1	Lin Yuan, Gang Qu 0001	Design Space Exploration for Energy-Efficient Secure Sensor Network.	ASAP	2002	DBLP DOI BibTeX RDF
1	Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli	Fast Radix-4 Retimed Division with Selection by Comparisons.	ASAP	2002	DBLP DOI BibTeX RDF
1	Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen	A Mathematical Model of Trace Cache.	ASAP	2002	DBLP DOI BibTeX RDF
1	Sumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna	A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs.	ASAP	2002	DBLP DOI BibTeX RDF	reconfigurable computing, embedded system design, energy optimization
1	Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall	Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.	ASAP	2002	DBLP DOI BibTeX RDF
1	David W. Matula, Alex Fit-Florea, Lee D. McFearin	Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup.	ASAP	2002	DBLP DOI BibTeX RDF
1	Manju Manjunathaiah, Graham M. Megson	Compositional Technique for Synthesising Multi-Phase Regular Arrays.	ASAP	2002	DBLP DOI BibTeX RDF
1	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.	ASAP	2002	DBLP DOI BibTeX RDF
1	Chang Yong Kang, Earl E. Swartzlander Jr.	An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis.	ASAP	2002	DBLP DOI BibTeX RDF
1	Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll	Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip.	ASAP	2002	DBLP DOI BibTeX RDF
1	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks.	ASAP	2002	DBLP DOI BibTeX RDF

Publications at "ASAP"( http://dblp.L3S.de/Venues/ASAP )