Search results for "Codesign"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Ignacio Peñarrocha, Daniel Dolz, Julio Ariel Romero, Roberto Sanchis 0001	State Estimation and Send on Delta Strategy Codesign for Networked Control Systems.	ICINCO (1)	2012	DBLP BibTeX RDF
16	Alan Gara	The long term impact of codesign.	SC Companion	2012	DBLP DOI BibTeX RDF
16	Fengwei An, Hans Jürgen Mattausch	Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign.	PDCAT	2012	DBLP DOI BibTeX RDF
16	Reimund Klemm	HW-SW-Codesign für effiziente bitstromorientierte Datenverarbeitung eingebetteter Systeme.		2012	RDF
16	Pauline Trouvé	Conception conjointe optique/traitement pour un imageur compact à capacité 3D. (Digital-optical codesign of an imaging system with 3D ability).		2012	RDF
16	Elizabeth I. Leonard, Myla Archer, Constance L. Heitmeyer, Ralph D. Jeffords	Direct generation of invariants for reactive models.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Aryan Arbabi, Milad Gholami, Mojtaba Varmazyar, Shervin Daneshpajouh	Fast CPU-based DNA exact sequence aligner.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Heinz Riener, Görschwin Fey	Model-based diagnosis versus error explanation.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Gideon Smeding, Gregor Gößler	A correlation preserving performance analysis for stream processing systems.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Asif Khan 0005, Muralidaran Vijayaraghavan, Arvind	A general technique for deterministic model-cycle-level debugging.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu	Improving design verifiability by early RTL coverability analysis.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Daniel E. Holcomb, Alexander Gotmanov, Michael Kishinevsky, Sanjit A. Seshia	Compositional performance verification of NoC designs.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Yosinori Watanabe, Stuart Swan	Clearing the clutter: Unified modeling and verification methodology for system level hardware design.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Kartik Nagar, Y. N. Srikant	Interdependent cache analyses for better precision and safety.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Yu Bai 0003, Jens Brandt 0001, Klaus Schneider 0001	Preservation of LTL properties in desynchronized systems.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita	Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Manuel Gesell, Klaus Schneider 0001	Interactive verification of synchronous systems.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno	Shepard: A fast exact match short read aligner.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Jiong Gong, Yun Wang, Haihao Shen, Xu Deng, Wei Wang, Xiangning Ma	FAST: Formal specification driven test harness generation.	MEMOCODE	2012	DBLP DOI BibTeX RDF
16	Petri Liuha, Kari Pehkonen, Juhani Rummukainen, Veli-Pekka Vatula, Tatu Koljonen	Research issues in smart phones, notepads and related services.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Giuseppe Di Guglielmo, Graziano Pravadelli	A testbench specification language for SystemC verification.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Carlo Brandolese, William Fornaciari, Luigi Rucco, Federico Terraneo	Enabling ultra-low power operation in high-end wireless sensor networks nodes.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Shih-Hao Hung, Chi-Sheng Shih 0001, Tei-Wei Kuo, Chia-Heng Tu, Che-Wei Chang	A real-time, energy-efficient system software suite for heterogeneous multicore platforms.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Lide Zhang, Mark S. Gordon, Robert P. Dick, Zhuoqing Morley Mao, Peter A. Dinda, Lei Yang 0017	ADEL: an automatic detector of energy leaks for smartphone applications.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Randolf Mock, Moritz Neukirchner, Rolf Ernst, Ruud Wijtvliet, Michael Huetwohl, Pascal Urard, Ovidiu Vermesan	Internet-of-energy: combining embedded computing and communication for the smart grid.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Carlo Brandolese, William Fornaciari	Software energy optimization through fine-grained function-level voltage and frequency scaling.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Martin Lukasiewycz, Samarjit Chakraborty	Concurrent architecture and schedule optimization of time-triggered automotive systems.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Mohamed Bamakhrama, Todor P. Stefanov	Managing latency in embedded streaming applications under hard-real-time scheduling.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu	A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto	Knowledge-based design space exploration of wireless sensor networks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Xuejing He, Robert P. Dick, Russ Joseph	Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Peter van Stralen, Andy D. Pimentel	A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Ralf Dreesen	Generating interlocked instruction pipelines from specifications of instruction sets.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Luc Michel, Nicolas Fournel, Frédéric Pétrot	Fast simulation of systems embedding VLIW processors.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Satnam Singh	Computing without processors.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Edoardo Paone, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley	An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Ciprian Seiculescu, Luca Benini, Giovanni De Micheli	A distributed interleaving scheme for efficient access to WideIO DRAM memory.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee	SystemC simulation on GP-GPUs: CUDA vs. OpenCL.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Garo Bournoutian, Alex Orailoglu	Dynamic transient fault detection and recovery for embedded processor datapaths.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran	DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Tom Vander Aa, Panagiotis Theocharis	Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Dan Gunnarsson, Stefan Kuntz, Glenn Farrall, Akihito Iwai, Rolf Ernst	Trends in automotive embedded systems.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Daniel Lorenz 0002, Kim Grüttner, Nicola Bombieri, Valerio Guarnieri, Sara Bocchio	From RTL IP to functional system-level models with extra-functional properties.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Ang Li, Mingsong Chen	Efficient self-learning techniques for SAT-based test generation.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Chen Huang 0005, Bailey Miller, Frank Vahid, Tony Givargis	Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Viraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan	Using static analysis for coverage extraction fromemulation/prototyping platforms.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Daniel Cordes, Michael Engel, Peter Marwedel, Olaf Neugebauer	Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Thomas Ebi, Hussam Amrouch, Jörg Henkel	COOL: control-based optimization of load-balancing for thermal behavior.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Marcio F. da S. Oliveira, Christoph Kuznik, Hoang Minh Le 0001, Daniel Große, Finn Haedicke, Wolfgang Müller 0003, Rolf Drechsler, Wolfgang Ecker, Volkan Esen	The system verification methodology for advanced TLM verification.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann	Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev	Minimizing power supply noise through harmonic mappings in networks-on-chip.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Zhonglei Wang, Jörg Henkel	HyCoS: hybrid compiled simulation of embedded software with target dependent code.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Fabian Oboril, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori	Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Hannu Kauppinen	Wireless innovations for smartphones.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Sungpack Hong, Tayo Oguntebi, Jared Casper, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun	A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Jingqing Mu, Roman L. Lysecky	Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal	Worst-case throughput analysis of real-time dynamic streaming applications.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Kyoungwoo Lee, Aviral Shrivastava, Reiley Jeyapaul	Soft errors: the hardware-software interface.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero 0002, Raúl Valencia	A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Shahzad Ahmad Butt, Luciano Lavagno	Designing parameterized signal processing ips for high level synthesis in a model based design environment.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli	Dynamic property mining for embedded software.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Erwin de Kock, Jos Verhaegh, Serge Amougou	A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Muhammad Usman Karim Khan, Muhammad Shafique 0001, Jörg Henkel	A hierarchical control scheme for energy quota distribution in hybrid distributed video coding.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Adam S. Hartman, Donald E. Thomas	Lifetime improvement through runtime wear-based task mapping.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Jong-Deok Choi	A standards-based, fully-open software platform for smart embedded systems.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Dongwook Lee, Hyungman Park, Andreas Gerstlauer	Synthesis of optimized hardware transactors from abstract communication specifications.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Gaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio, Minglun Gao	Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Mohammad Sajjad Hossain, Woo Suk Lee, Vijay Raghunathan	SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Chantal Ykman-Couvreur, Philipp A. Hartmann, Gianluca Palermo, Fabien Colas-Bigey, Laurent San	Run-time resource management based on design space exploration.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta	Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Daniel T. Grissom, Philip Brisk	Fast online synthesis of generally programmable digital microfluidic biochips.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	James Coole, Greg Stitt	BPR: fast FPGA placement and routing using macroblocks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Luis Angel D. Bathen, Mark Gottscho, Nikil D. Dutt, Alex Nicolau, Puneet Gupta 0001	ViPZonE: OS-level memory variability-driven physical address zoning for energy savings.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Parinaz Sayyah, Mihai T. Lazarescu, Davide Quaglia, Emad Samuel Malki Ebeid, Sara Bocchio, Alberto Rosti	Network-aware design-space exploration of a power-efficient embedded application.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Marcelo Sousa, Alper Sen 0001	Generation of TLM testbenches using mutation testing.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Domitian Tamas-Selicean, Paul Pop, Wilfried Steiner	Synthesis of communication schedules for TTEthernet-based mixed-criticality systems.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Haeseung Lee, Weijia Che, Karam S. Chatha	Dynamic scheduling of stream programs on embedded multi-core processors.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Andrea Tilli, Andrea Bartolini, Matteo Cacciari, Luca Benini	Don't burn your mobile!: safe computational re-sprinting via model predictive control.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu	SystemC as completing pillar in industrial OVM based verification environments.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Wonwoo Jung, Chulkoo Kang, Chanmin Yoon, Dongwon Kim, Hojung Cha	DevScope: a nonintrusive and online power analysis tool for smartphone hardware components.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Ming-Chang Yang, Yuan-Hao Chang 0001, Po-Chun Huang, Tei-Wei Kuo	Working-set-based address mapping for ultra-large-scaled flash devices.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Wolfgang Müller 0003, Wolfgang Ecker	Testbenches for advanced TLM verification.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Abbas BanaiyanMofrad, Gustavo Girão, Nikil D. Dutt	A novel NoC-based design for fault-tolerance of last-level caches in CMPs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Pranab Roy, Rupam Bhattacharjee, Modud Sohid, Sudipta Chakraborty, Hafizur Rahaman 0001, Parthasarathi Dasgupta	An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Kazuyuki Tanimura, Nikil D. Dutt	LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Miguel Salas, Sudeep Pasricha	The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routers.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Octavian Cheng, Waleed H. Abdulla, Zoran A. Salcic	Hardware-Software Codesign of Automatic Speech Recognition System for Embedded Real-Time Applications.	IEEE Trans. Ind. Electron.	2011	DBLP DOI BibTeX RDF
16	Lesley Shannon, Paul Chow	Leveraging reconfigurability in the hardware/software codesign process.	ACM Trans. Reconfigurable Technol. Syst.	2011	DBLP DOI BibTeX RDF
16	Koichi Tokuno, Shigeru Yamada	Codesign-Oriented Performability Modeling for Hardware-Software Systems.	IEEE Trans. Reliab.	2011	DBLP DOI BibTeX RDF
16	Yin-Tsung Hwang, Cheng-Chen Lin, Ruei-Ting Hung	Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign.	IEEE Embed. Syst. Lett.	2011	DBLP DOI BibTeX RDF
16	Ren-Jie Lee, Hung-Ming Chen	Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
16	Darren J. Kerbyson, Abhinav Vishnu, Kevin J. Barker, Adolfy Hoisie	Codesign Challenges for Exascale Systems: Performance, Power, and Reliability.	Computer	2011	DBLP DOI BibTeX RDF
16	John Shalf, Daniel J. Quinlan, Curtis L. Janssen	Rethinking Hardware-Software Codesign for Exascale Systems.	Computer	2011	DBLP DOI BibTeX RDF
16	Vladimir Getov, Adolfy Hoisie, Harvey J. Wasserman	Codesign for Systems and Applications: Charting the Path to Exascale Computing.	Computer	2011	DBLP DOI BibTeX RDF
16	Sayantan Sur, Sreeram Potluri, Krishna Chaitanya Kandalla, Hari Subramoni, Dhabaleswar K. Panda 0001, Karen Tomko	Codesign for InfiniBand Clusters.	Computer	2011	DBLP DOI BibTeX RDF
16	Rajdeep Bondade, Dongsheng Ma 0001	Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
16	Grant Martin	Will hardware and software be codesigned? [review of "A Practical Introduction to Hardware/Software Codesign" (Schaumont, P.R.; 2010)].	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF
16	Satnam Singh, Barbara Jobstmann, Michael Kishinevsky, Jens Brandt 0001 (eds.)	9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011	MEMOCODE	2011	DBLP BibTeX RDF
16	Emeric de Foucauld, Jean-Baptiste David, Christophe Delaveaud, Pascal Ciais	An antenna-filter codesign for cardiac implants.	DATE	2011	DBLP DOI BibTeX RDF
16	Sanad Al-Areqi, Daniel Görges, Steven Liu	Robust control and scheduling codesign for networked embedded control systems.	CDC/ECC	2011	DBLP DOI BibTeX RDF