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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 700 occurrences of 376 keywords
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Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Jong Beom Park, William Rhett Davis, Paul D. Franzon |
3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Goran HamaAli, Diary R. Sulaiman, Muhammed A. Ibrahim |
Power and thermal management in SRAM and DRAM using adaptive body biasing technique. |
IEICE Electron. Express |
2019 |
DBLP DOI BibTeX RDF |
|
13 | André Schaller, Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Boris Skoric, Stefan Katzenbeisser 0001, Jakub Szefer |
Decay-Based DRAM PUFs in Commodity Devices. |
IEEE Trans. Dependable Secur. Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Jinyu Zhan, Junhuan Yang, Wei Jiang 0016, Yufang Sun, Yixin Li |
Vehicle data management with specific wear-levelling and fault tolerance for hybrid DRAM-NVM memory. |
J. Syst. Archit. |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sheel Sindhu Manohar, Hemangee K. Kapoor |
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation. |
J. Syst. Archit. |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Xing Pan, Frank Mueller 0001 |
The Colored Refresh Server for DRAM. |
ISORC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Minesh Patel, Jeremie S. Kim, Hasan Hassan, Onur Mutlu |
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices. |
DSN |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Haonan Wang, Adwait Jog |
Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM. |
DSN |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung 0001, Norbert Wehn |
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. |
SAMOS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sherif M. Sharroush |
A Novel Current-Domain DRAM Readout Scheme. |
ICM |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Mohamed Hassan 0002 |
Managing DRAM Interference in Mixed Criticality Embedded Systems. |
ICM |
2019 |
DBLP DOI BibTeX RDF |
|
13 | David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic |
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. |
FPGA |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Zhiyuan Shao, Ruoshi Li, Diqing Hu, Xiaofei Liao, Hai Jin 0001 |
Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching. |
FPGA |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sheel Sindhu Manohar, Hemangee K. Kapoor |
Refresh optimised embedded-dram caches based on zero data detection. |
SAC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Nam-Hyun Lee, Jongkyun Kim, Donghee Son, Kangjun Kim, Jung Eun Seok |
Comprehensive Study for OFF-State Hot Carrier Degrdation of Scaled nMOSFETs in DRAM. |
IRPS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | KyungWoo Lee, Chae-Hyuk Yun, HyungAh Seo, Taehun Kang, Yunsung Lee, Kangyong Cho |
An Evaluation of X-Ray Irradiation Induced Dynamic Refresh Characterization in DRAM. |
IRPS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sheng Ma, Yang Guo 0003, Shenggang Chen, Libo Huang, Zhiying Wang 0003 |
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators. |
DATE |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser 0001, Jakub Szefer |
Spying on Temperature using DRAM. |
DATE |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Skanda Koppula, Lois Orosa 0001, Abdullah Giray Yaglikçi, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, Onur Mutlu |
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM. |
MICRO |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Wei-Hsuan Yang, Jin-Fu Li 0001, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang |
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. |
3DIC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa 0001, Onur Mutlu |
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput. |
HPCA |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki |
Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM. |
HPSR |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Reza Salkhordeh, André Brinkmann |
Online Management of Hybrid DRAM-NVMM Memory for HPC. |
HiPC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Bo Wang, Jie Tang 0003, Rui Zhang, Wei Ding, Shaoshan Liu, Deyu Qi 0001 |
Energy-Efficient Data Caching Framework for Spark in Hybrid DRAM/NVM Memory Architectures. |
HPCC/SmartCity/DSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Rakesh Pandey, Aryabartta Sahu |
Access-Aware Self-Adaptive Data Mapping onto 3D-Stacked Hybrid DRAM-PCM Based Chip-Multiprocessor. |
HPCC/SmartCity/DSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Ruicheng Liu, Peiquan Jin, Zhangling Wu, Xiaoliang Wang, Shouhong Wan, Bei Hua |
Efficient Wear Leveling for PCM/DRAM-Based Hybrid Memory. |
HPCC/SmartCity/DSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Haiyang Pan, Yuhang Liu 0001, Tianyue Lu, Mingyu Chen 0001 |
Characterizations and Architectural Implications of NVM's External DRAM Cache. |
HPCC/SmartCity/DSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Anirban Chakraborty 0003, Manaar Alam, Debdeep Mukhopadhyay |
Deep Learning Based Diagnostics for Rowhammer Protection of DRAM Chips. |
ATS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shuqi Yu, Linmei Hu, Bin Wu 0001 |
DRAM: A Deep Reinforced Intra-attentive Model for Event Prediction. |
KSEM (1) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Jongbok Lee |
DRAM Effects on the Embedded Processor Performance. |
ICEIC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Mikhail Asiatici, Paolo Ienne |
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Saugata Ghose, Tianshi Li 0001, Nastaran Hajinazar, Damla Senol Cali, Onur Mutlu |
Demystifying Complex Workload-DRAM Interactions: An Experimental Study. |
SIGMETRICS (Abstracts) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Tobi Delbrück, Shih-Chii Liu |
Data-Driven Neuromorphic DRAM-based CNN and RNN Accelerators. |
ACSSC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Mikhail Zarubin, Patrick Damme, Thomas Kissinger, Dirk Habich, Wolfgang Lehner, Thomas Willhalm |
Integer Compression in NVRAM-centric Data Stores: Comparative Experimental Analysis to DRAM. |
DaMoN |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Georgios Psaropoulos, Ismail Oukid, Thomas Legler, Norman May, Anastasia Ailamaki |
Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations. |
DaMoN |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Wen Pan, Tao Xie 0004, Xiaojia Song |
HART: A Concurrent Hash-Assisted Radix Tree for DRAM-PM Hybrid Memory Systems. |
IPDPS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Matthias Jung 0001, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn |
Fast validation of DRAM protocols with timed petri nets. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Onkar Patil, Latchesar Ionkov, Jason Lee, Frank Mueller 0001, Michael Lang 0003 |
Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Darko Zivanovic, Pouya Esmaili-Dokht, Sergi Moré, Javier Bartolome, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé |
DRAM errors in the field: a statistical approach. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shang Li 0001, Rommel Sánchez Verdejo, Petar Radojkovic, Bruce L. Jacob |
Rethinking cycle accurate DRAM simulation. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad M. Rafique, Zhichun Zhu |
FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shang Li 0001, Bruce L. Jacob |
Statistical DRAM modeling. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sebastian Werner 0002, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan |
3D photonics as enabling technology for deep 3D DRAM stacking. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Anup Sarma, Huaipan Jiang, Ashutosh Pattnaik, Jagadish Kotra, Mahmut Taylan Kandemir, Chita R. Das |
CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli |
Quality Aware Selective ECC for Approximate DRAM. |
ApplePies |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Cheng-Hsuan Cheng, Ren-Shuo Liu |
AIP: Saving the DRAM Access Energy of CNNs Using Approximate Inner Products. |
AICAS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sven Müelich, Sebastian Bitzer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Martin Bossert, Robert F. H. Fischer |
Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements. |
REDUNDANCY |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Se Kwon Lee, Jayashree Mohan, Sanidhya Kashyap, Taesoo Kim, Vijay Chidambaram |
Recipe: converting concurrent DRAM indexes to persistent-memory indexes. |
SOSP |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim |
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. |
ICCAD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shaahin Angizi, Deliang Fan |
ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations. |
ICCAD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Thales Bandiera Paiva, Javier Navaridas, Routo Terada |
Robust Covert Channels Based on DRAM Power Consumption. |
ISC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Xing Pan, Frank Mueller 0001 |
Hiding DRAM Refresh Overhead in Real-Time Cyclic Executives. |
RTSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Xing Pan, Frank Mueller 0001 |
The Colored Refresh Server for DRAM. |
RTSS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Seong Ju Lee, Byung Deuk Jeon, Kyeong Pil Kang, Dong Yoon Ka, Na Yeon Kim, Yongseop Kim, Yunseok Hong, Mankeun Kang, Jinyong Min, Mingyu Lee, Chunseok Jeong, Kwandong Kim, Doobock Lee, Junghyun Shin, Yuntack Han, Youngbo Shim, Youngjoo Kim, Yongsun Kim, Hyunseok Kim, Jaewoong Yun, Byungsoo Kim, Seokhwan Han, Changwoo Lee, Junyong Song, Ho Uk Song, Il Park 0001, Yongju Kim, Junhyun Chun, Jonghoon Oh |
A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. |
ISSCC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Taegeun Yoo, Hyunjoon Kim, Qian Chen 0027, Tony Tae-Hyoung Kim, Bongjin Kim |
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. |
ISLPED |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Wang Xu, Israel Koren |
Designing a secure DRAM+NVM hybrid memory module. |
CF |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Chun Shiah, C. N. Chang, Richard Crisp, C. P. Lin, C. N. Pan, C. P. Chuang, H. L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu |
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. |
VLSI Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shuai Chen, Wenjie Xiong 0001, Yehan Xu, Bing Li, Jakub Szefer |
Thermal Covert Channels Leveraging Package-on-Package DRAM. |
TrustCom/BigDataSE |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yicheng Wang, Yang Liu 0114, Peiyun Wu, Zhao Zhang 0008 |
Reinforce Memory Error Protection by Breaking DRAM Disturbance Correlation Within ECC Words. |
ICCD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam |
Post-Model Validation of Victim DRAM Caches. |
ICCD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Vinson Young, Moinuddin K. Qureshi |
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches. |
ICCD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Vinson Young, Zeshan A. Chishti, Moinuddin K. Qureshi |
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems. |
ICCD |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung 0001, Norbert Wehn |
An In-DRAM Neural Network Processing Engine. |
ISCAS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Rhongho Jang, Seongkwang Moon, Youngtae Noh, Aziz Mohaisen, DaeHun Nyang |
InstaMeasure: Instant Per-flow Detection Using Large In-DRAM Working Set of Active Flows. |
ICDCS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Lev Mukhanov, Konstantinos Tovletoglou, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Georgios Karakonstantis |
Workload-Aware DRAM Error Prediction using Machine Learning. |
IISWC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor |
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. |
ACM Great Lakes Symposium on VLSI |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shaahin Angizi, Deliang Fan |
GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing. |
ACM Great Lakes Symposium on VLSI |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yu Ma, Linfeng Zheng, Pingqiang Zhou |
CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Ning Li, Wen-Yang Jiang, Blacksmith Wu, Kanyu Cao |
Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Donald Kline Jr., Stephen Longofono, Rami G. Melhem, Alex K. Jones |
Predicting Single Event Effects in DRAM. |
DFT |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Kaustav Goswami 0002, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee |
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. |
ISQED |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Duy Thanh Nguyen, Ik-Joon Chang |
Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection. |
ISOCC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Chundian Li, Mingzhe Zhang, Zhiwei Xu, Xianhe Sun |
Self-Adaptive Address Mapping Mechanism for Access Pattern Awareness on DRAM. |
ISPA/BDCloud/SocialCom/SustainCom |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Liu Yang, Peiquan Jin, Shouhong Wan |
BF-Join: An Efficient Hash Join Algorithm for DRAM-NVM-Based Hybrid Memory Systems. |
ISPA/BDCloud/SocialCom/SustainCom |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Gabor Csordas, Mikhail Asiatici, Paolo Ienne |
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. |
FPT |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yiming Zhu |
What are the driving forces of DRAM? |
A-SSCC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Bashir M. Sabquat Bahar Talukder, Joseph Kerns, Biswajit Ray, Thomas H. Morris, Md. Tauhidur Rahman 0001 |
Exploiting DRAM Latency Variations for Generating True Random Numbers. |
ICCE |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Hasan Hassan, Minesh Patel, Jeremie S. Kim, Abdullah Giray Yaglikçi, Nandita Vijaykumar, Nika Mansouri-Ghiasi, Saugata Ghose, Onur Mutlu |
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability. |
ISCA |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Xin-Chuan Wu, Timothy Sherwood, Frederic T. Chong, Yanjing Li |
Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells. |
ASPLOS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Mahdi Nazm Bojnordi, Farhan Nasrullah |
ReTagger: An Efficient Controller for DRAM Cache Architectures. |
DAC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Duy Thanh Nguyen, Nhut-Minh Ho, Ik-Joon Chang |
St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs. |
DAC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Xin Xin 0008, Youtao Zhang, Jun Yang 0002 |
ROC: DRAM-based Processing with Reduced Operation Cycles. |
DAC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang 0002 |
LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator. |
DAC |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Gaspar Tognetti, Jonah Sengupta, Philippe O. Pouliquen, Andreas G. Andreou |
Characterization of a pseudo-DRAM Crossbar Computational Memory Array in 55nm CMOS : (Invited Paper). |
CISS |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Rhongho Jang, Seongkwang Moon, Youngtae Noh, Aziz Mohaisen, DaeHun Nyang |
A cost-effective anomaly detection system using in-DRAM working set of active flows table: poster. |
WiSec |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Saugata Ghose, Abdullah Giray Yaglikçi, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu |
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study. |
Proc. ACM Meas. Anal. Comput. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park |
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. |
IEEE J. Solid State Circuits |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman |
An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. |
IEEE J. Solid State Circuits |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stephan Rau, Michael Richter 0003, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale |
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. |
IEEE J. Solid State Circuits |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Seikwon Kim, Wonsang Kwak, Changdae Kim, Jaehyuk Huh 0001 |
Zebra Refresh: Value Transformation for Zero-Aware DRAM Refresh Reduction. |
IEEE Comput. Archit. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang |
Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM. |
IEEE Comput. Archit. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Jitae Yun, Su-Kyung Yoon, Jeong-Geun Kim, Bernd Burgstaller, Shin-Dug Kim |
Regression Prefetcher with Preprocessing for DRAM-PCM Hybrid Main Memory. |
IEEE Comput. Archit. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam |
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. |
IEEE Comput. Archit. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser 0001, John A. Chandy, Fatemeh Tehranipoor |
An Overview of DRAM-Based Security Primitives. |
Cryptogr. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Larry Pearlstein, Skyler Maxwell, Alex Aved |
Adaptive prediction resolution video coding for reduced DRAM bandwidth. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Sukhan Lee 0002, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim, Jung Ho Ahn |
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. |
IEEE Access |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zongwei Zhu, Jing Cao, Xi Li 0003, Junneng Zhang, Youqing Xu, Gangyong Jia |
Impacts of Memory Address Mapping Scheme on Reducing DRAM Self-Refresh Power for Mobile Computing Devices. |
IEEE Access |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Su-Kyung Yoon, Young-Sun Youn, Jeong-Geun Kim, Shin-Dug Kim |
Design of DRAM-NAND flash hybrid main memory and Q-learning-based prefetching method. |
J. Supercomput. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki 0001, Katsuki Fujisawa |
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. |
IEICE Trans. Inf. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Miseon Han, Yeoul Na, Dongha Jung, Hokyoon Lee, Seon Wook Kim, Youngsun Han |
Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB. |
IEICE Trans. Electron. |
2018 |
DBLP DOI BibTeX RDF |
|
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