Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason D. Bakos	FPGA Acceleration of Gene Rearrangement Analysis.	FCCM	2007	DBLP DOI BibTeX RDF
1	Kyle Rupnow, Keith D. Underwood, Katherine Compton	Scientific Application Acceleration with Reconfigurable Functional Units.	FCCM	2007	DBLP DOI BibTeX RDF
1	Yongfeng Gu, Martin C. Herbordt	FPGA-Based Multigrid Computation for Molecular Dynamics Simulations.	FCCM	2007	DBLP DOI BibTeX RDF
1	Volodymyr V. Kindratenko, Robert J. Brunner, Adam D. Myers	Mitrion-C Application Development on SGI Altix 350/RC100.	FCCM	2007	DBLP DOI BibTeX RDF
1	Charles Ross, A. P. Wim Böhm	The Case for Dynamic Execution on Dynamic Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain	FPGA-accelerated seed generation in Mercury BLASTP.	FCCM	2007	DBLP DOI BibTeX RDF
1	Adam Megacz	A Library and Platform for FPGA Bitstream Manipulation.	FCCM	2007	DBLP DOI BibTeX RDF
1	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung	A Hybrid Memory Sub-system for Video Coding Applications.	FCCM	2007	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
1	Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung	Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Kenneth L. Pocek, Duncan A. Buell (eds.)	IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA	FCCM	2007	DBLP BibTeX RDF
1	Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King	Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
1	I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler	Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.	FCCM	2007	DBLP DOI BibTeX RDF
1	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A Flexible Filter Processor for Fading Channel Simulation.	FCCM	2007	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Automatic On-chip Memory Minimization for Data Reuse.	FCCM	2007	DBLP DOI BibTeX RDF
1	Rui Rodrigues 0004, João M. P. Cardoso, Pedro C. Diniz	A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.	FCCM	2007	DBLP DOI BibTeX RDF
1	Christoforos Kachris, Chidamber Kulkarni	Configurable Transactional Memory.	FCCM	2007	DBLP DOI BibTeX RDF
1	Tim Güneysu, Bodo Möller, Christof Paar	New Protection Mechanisms for Intellectual Property in Reconfigurable Logic.	FCCM	2007	DBLP DOI BibTeX RDF
1	Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood	Changing Output Quality for Thermal Management.	FCCM	2007	DBLP DOI BibTeX RDF
1	Grigorios Chrysos 0001, Apostolos Dollas, Nikolaos G. Bourbakis, J. Sukarno Mertoguno	An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology.	FCCM	2007	DBLP DOI BibTeX RDF
1	Giacomo de Meulenaer, François Gosset, Guerric Meurice de Dormale, Jean-Jacques Quisquater	Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
1	Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann	Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip.	FCCM	2007	DBLP DOI BibTeX RDF
1	Thomas Eisenbarth 0001, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier	Establishing Chain of Trust in Reconfigurable Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
1	Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson	Generating FPGA-Accelerated DFT Libraries.	FCCM	2007	DBLP DOI BibTeX RDF
1	Chris Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang	Low-Cost Stereo Vision on an FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
1	Michael Butts, Anthony Mark Jones, Paul Wasson	A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing.	FCCM	2007	DBLP DOI BibTeX RDF
1	Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos	A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem.	FCCM	2007	DBLP DOI BibTeX RDF
1	Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka	Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing.	FCCM	2007	DBLP DOI BibTeX RDF
1	J. Javier Martínez-Álvarez, F. Javier Toledo-Moreo, José Manuel Ferrández de Vicente	Discrete-Time Cellular Neural Networks in FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, Ron Sass	Quantifying Effective Memory Bandwidth of Platform FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Xiaojun Wang, Miriam Leeser	K-means Clustering for Multispectral Images Using Floating-Point Divide.	FCCM	2007	DBLP DOI BibTeX RDF
1	Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi	A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.	FCCM	2007	DBLP DOI BibTeX RDF
1	David Castells-Rufas, Jordi Carrabina	Jumble: A Hardware-in-the-Loop Simulation System for JHDL.	FCCM	2007	DBLP DOI BibTeX RDF
1	Graham Schelle, Dirk Grunwald	Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources.	FCCM	2007	DBLP DOI BibTeX RDF
1	F. Javier Toledo-Moreo, J. Javier Martínez-Álvarez, José Manuel Ferrández de Vicente	Hand-based Interface for Augmented Reality.	FCCM	2007	DBLP DOI BibTeX RDF
1	Philip Garcia, Katherine Compton	A Reconfigurable Hardware Interface for a Modern Computing System.	FCCM	2007	DBLP DOI BibTeX RDF
1	Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns	Hardware/Software co-design of a key point detector on FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
1	Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater	On Solving RC5 Challenges with FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi	A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic.	FCCM	2007	DBLP DOI BibTeX RDF
1	Kushal Datta, Ron Sass	RBoot: Software Infrastructure for a Remote FPGA Laboratory.	FCCM	2007	DBLP DOI BibTeX RDF
1	Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli	Sparse Matrix-Vector Multiplication Design on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Proshanta Saha, Tarek A. El-Ghazawi	Software/Hardware Co-Scheduling for Reconfigurable Computing Systems.	FCCM	2007	DBLP DOI BibTeX RDF
1	Kyprianos Papadimitriou, Antonis Anyfantis, Apostolos Dollas	Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead.	FCCM	2007	DBLP DOI BibTeX RDF
1	Haohuan Fu, Oskar Mencer, Wayne Luk	Optimizing Logarithmic Arithmetic on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan	Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems.	FCCM	2007	DBLP DOI BibTeX RDF
1	Ronen Goldberg, Guy Even, Peter-Michael Seidel	An FPGA implementation of pipelined multiplicative division with IEEE Rounding.	FCCM	2007	DBLP DOI BibTeX RDF
1	Zachary K. Baker, Maya B. Gokhale	On the Acceleration of Shortest Path Calculations in Transportation Networks.	FCCM	2007	DBLP DOI BibTeX RDF
1	Kentaro Sano, Takanori Iizuka, Satoru Yamamoto	Systolic Architecture for Computational Fluid Dynamics on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Euripides Sotiriades, Apostolos Dollas	Design Space Exploration for the BLAST Algorithm Implementation.	FCCM	2007	DBLP DOI BibTeX RDF
1	Neil W. Bergmann, Yi Lu 0004, John A. Williams 0001	Automatic Self-Reconfiguration of System-on-Chip Peripherals.	FCCM	2007	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	Efficient Hardware Generation of Random Variates with Arbitrary Distributions.	FCCM	2006	DBLP DOI BibTeX RDF
1	Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams 0001	VPN Acceleration Using Reconfigurable System-On-Chip Technology.	FCCM	2006	DBLP DOI BibTeX RDF
1	Gerhard Lienhart, Guillermo Marcus Martinez, Andreas Kugel, Reinhard Männer	Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics.	FCCM	2006	DBLP DOI BibTeX RDF
1	K. N. Vikram, Vinita Vasudevan	Scheduling divisible loads on partially reconfigurable hardware.	FCCM	2006	DBLP DOI BibTeX RDF
1	Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier	Template-Based Generation of Streaming Accelators from a High Level Presentation.	FCCM	2006	DBLP DOI BibTeX RDF
1	Andrey Bogdanov, M. C. Mertens, Christof Paar, Jan Pelzl, Andy Rupp	A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2).	FCCM	2006	DBLP DOI BibTeX RDF
1	Shannon Koh, Oliver Diessel	COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Volodymyr V. Kindratenko, David Pointer	A case study in porting a production scientific supercomputing application to a reconfigurable computer.	FCCM	2006	DBLP DOI BibTeX RDF
1	Kendall Ananyi, Daler N. Rakhmatov	Design of a Reconfigurable Processor for NIST Prime Field ECC.	FCCM	2006	DBLP DOI BibTeX RDF
1	David J. Lau, Orion Pritchard, Philippe Molson	Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions.	FCCM	2006	DBLP DOI BibTeX RDF
1	Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan	Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.	FCCM	2006	DBLP DOI BibTeX RDF
1	Martin C. Herbordt, Josh Model, Yongfeng Gu, Bharat Sukhwani, Tom Van Court	Single Pass, BLAST-Like, Approximate String Matching on FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Dionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas	Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration.	FCCM	2006	DBLP DOI BibTeX RDF
1	Michael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather	Floating-Point Accumulation Circuit for Matrix Applications.	FCCM	2006	DBLP DOI BibTeX RDF
1	Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Régis Pomès, Paul Chow	A Scalable FPGA-based Multiprocessor.	FCCM	2006	DBLP DOI BibTeX RDF
1	Zachary K. Baker, Viktor K. Prasanna	An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems.	FCCM	2006	DBLP DOI BibTeX RDF
1	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
1	Matthew French, Li Wang 0012, Michael J. Wirthlin	Power Visualization, Analysis, and Optimization Tools for FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Chuan He, Guan Qin, Mi Lu, Wei Zhao 0001	An Optimized Finite Difference Computing Engine on FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Xiaojun Wang, Sherman Braganza, Miriam Leeser	Advanced Components in the Variable Precision Floating-Point Library.	FCCM	2006	DBLP DOI BibTeX RDF
1	Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann	FPGAs, GPUs and the PS2 - A Single Programming Methodology.	FCCM	2006	DBLP DOI BibTeX RDF
1	Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna	Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers.	FCCM	2006	DBLP DOI BibTeX RDF
1	Cao Liang, Jing Ma 0006, Xinming Huang 0001	Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms.	FCCM	2006	DBLP DOI BibTeX RDF
1	Allen Michalski, Duncan A. Buell	A Scalable Architecture for RSA Cryptography on Large FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	John A. Williams 0001, Irfan Syed, Jason Wu, Neil W. Bergmann	A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer.	FCCM	2006	DBLP DOI BibTeX RDF
1	Yongfeng Gu, Tom Van Court, Martin C. Herbordt	Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report.	FCCM	2006	DBLP DOI BibTeX RDF
1	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.	FCCM	2006	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho	Scalable Softcore Vector Processor for Biosequence Applications.	FCCM	2006	DBLP DOI BibTeX RDF
1	Jia Ming Mar, Alessandro Bissacco, Stefano Soatto, Soheil Ghiasi	High Performance Feature Detection on a Reconfigurable Co-Processor.	FCCM	2006	DBLP DOI BibTeX RDF
1	Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson	A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer.	FCCM	2006	DBLP DOI BibTeX RDF
1	K. Scott Hemmert, Keith D. Underwood	Open Source High Performance Floating-Point Modules.	FCCM	2006	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, reconfigurable computing
1	Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito	General Architecture for Hardware Implementation of Genetic Algorithm.	FCCM	2006	DBLP DOI BibTeX RDF
1	Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, John W. Lockwood	Hierarchical Clustering using Reconfigurable Devices.	FCCM	2006	DBLP DOI BibTeX RDF
1	Haiqian Yu, Miriam Leeser	Automatic Sliding Window Operation Optimization for FPGA-Based.	FCCM	2006	DBLP DOI BibTeX RDF
1	Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon	GraphStep: A System Architecture for Sparse-Graph Algorithms.	FCCM	2006	DBLP DOI BibTeX RDF
1	Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez	Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures.	FCCM	2006	DBLP DOI BibTeX RDF
1	Brad Matthews, Itamar Elhanany	Scalable Hardware Architecture for Real-Time Dynamic Programming Applications.	FCCM	2006	DBLP DOI BibTeX RDF
1	Michael J. Wirthlin, Welson Sun	DSynth: A Pipeline Synthesis Environment for FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan	Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices.	FCCM	2006	DBLP DOI BibTeX RDF
1	Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman	Switch Box Architectures for Three-Dimensional FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul S. Graham, Maya B. Gokhale	The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability.	FCCM	2006	DBLP DOI BibTeX RDF
1	Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews 0001	Enabling a Uniform Programming Model Across the Software/Hardware Boundary.	FCCM	2006	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
1	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.	FCCM	2006	DBLP DOI BibTeX RDF
1	James Moscola, Young H. Cho, John W. Lockwood	A Scalable Hybrid Regular Expression Pattern Matcher.	FCCM	2006	DBLP DOI BibTeX RDF
1	Michael Attig, Gordon J. Brebner	Systematic Characterization of Programmable Packet Processing Pipelines.	FCCM	2006	DBLP DOI BibTeX RDF
1	Tom Van Court, Martin C. Herbordt	Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations.	FCCM	2006	DBLP DOI BibTeX RDF
1	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).	FCCM	2006	DBLP DOI BibTeX RDF
1	Kyprianos Papademetriou, Apostolos Dollas	A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems.	FCCM	2006	DBLP DOI BibTeX RDF
1	Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas	Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs.	FCCM	2006	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )