Search results for "FPT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Husain Parvez, Zied Marrakchi, Habib Mehrez	ASIF: Application Specific Inflexible FPGA.	FPT	2009	DBLP DOI BibTeX RDF
1	John D. Bunton	ASKAP beamformer.	FPT	2009	DBLP DOI BibTeX RDF
1	Daniel Le Ly, Manuel Saldaña, Paul Chow	The challenges of using an embedded MPI for hardware-based processing nodes.	FPT	2009	DBLP DOI BibTeX RDF
1	David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis	Rapid synthesis and simulation of computational circuits in an MPPA.	FPT	2009	DBLP DOI BibTeX RDF
1	Muhammad Shafiq 0003, Miquel Pericàs, Raúl de la Cruz, Mauricio Araya-Polo, Nacho Navarro, Eduard Ayguadé	Exploiting memory customization in FPGA for 3D stencil computations.	FPT	2009	DBLP DOI BibTeX RDF
1	Tim Güneysu, Christof Paar	Transforming write collisions in block RAMs into security applications.	FPT	2009	DBLP DOI BibTeX RDF
1	Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne	A flexible DSP block to enhance FPGA arithmetic performance.	FPT	2009	DBLP DOI BibTeX RDF
1	Xiao Dong, Guy G. F. Lemieux	PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess.	FPT	2009	DBLP DOI BibTeX RDF
1	Neil W. Bergmann, Oliver Diessel, Lesley Shannon (eds.)	Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009	FPT	2009	DBLP BibTeX RDF
1	Chia-Ching Tung, Ruchi B. Rungta, Eric Peskin	Simulation of a QCA-based CLB and a multi-CLB application.	FPT	2009	DBLP DOI BibTeX RDF
1	Lifan Yao, Hao Feng, Yiqun Zhu, Zhiguo Jiang, Danpei Zhao, Wenquan Feng	An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher.	FPT	2009	DBLP DOI BibTeX RDF
1	Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong	A detailed delay path model for FPGAs.	FPT	2009	DBLP DOI BibTeX RDF
1	Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung	Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.	FPT	2009	DBLP DOI BibTeX RDF
1	Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker 0001, Klaus D. Müller-Glaser	Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware.	FPT	2009	DBLP DOI BibTeX RDF
1	Gordon J. Brebner	Packets everywhere: The great opportunity for field programmable technology.	FPT	2009	DBLP DOI BibTeX RDF
1	Paul Beckett	Towards a balanced ternary FPGA.	FPT	2009	DBLP DOI BibTeX RDF
1	Benjamin Gojman, André DeHon	VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems.	FPT	2009	DBLP DOI BibTeX RDF
1	Neil Hockert, Katherine Compton	FFPU: Fractured floating point unit for FPGA soft processors.	FPT	2009	DBLP DOI BibTeX RDF
1	Donald G. Bailey, Christos-Savvas Bouganis	Implementation of a foveal vision mapping.	FPT	2009	DBLP DOI BibTeX RDF
1	James W. Crouch, Hiren J. Patel, Yong C. Kim, Jeffrey Todd McDonald, Tony C. Kim	Creating digital fingerprints on commercial field programmable gate arrays.	FPT	2008	DBLP DOI BibTeX RDF
1	Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong	Unrolling-based loop mapping and scheduling.	FPT	2008	DBLP DOI BibTeX RDF
1	Ahmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan	Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier.	FPT	2008	DBLP DOI BibTeX RDF
1	Audip Pandit, Lakshmi Easwaran, Ali Akoglu	Concurrent timing based and routability driven depopulation technique for FPGA packing.	FPT	2008	DBLP DOI BibTeX RDF
1	Xiang Tian 0001, Khaled Benkrid	Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer.	FPT	2008	DBLP DOI BibTeX RDF
1	Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays.	FPT	2008	DBLP DOI BibTeX RDF
1	Yoshifumi Tanida, Tsutomu Maruyama	An approach for downscaling images for real-time pattern detection.	FPT	2008	DBLP DOI BibTeX RDF
1	Wei Zhang, Vaughn Betz, Jonathan Rose	Portable and scalable FPGA-based acceleration of a direct linear system solver.	FPT	2008	DBLP DOI BibTeX RDF
1	Ali Irturk, Bridget Benson, Arash Arfaee, Ryan Kastner	Automatic generation of decomposition based matrix inversion architectures.	FPT	2008	DBLP DOI BibTeX RDF
1	Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan, Kris Gaj	Memory security management for reconfigurable embedded systems.	FPT	2008	DBLP DOI BibTeX RDF
1	Stephan Wong, Thijs van As, Geoffrey Brown	p-VEX: A reconfigurable and extensible softcore VLIW processor.	FPT	2008	DBLP DOI BibTeX RDF
1	Iakovos Mavroidis, Ioannis Papaefstathiou	Accelerating hardware simulation: Testbench code emulation.	FPT	2008	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Esti Stein	Extending Booth algorithm to multiplications of three numbers on FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Takayuki Mabuchi, Minoru Watanabe	An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays.	FPT	2008	DBLP DOI BibTeX RDF
1	Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system.	FPT	2008	DBLP DOI BibTeX RDF
1	Samuel Antao, Ricardo Chaves, Leonel Sousa	Efficient FPGA elliptic curve cryptographic processor over GF(2m).	FPT	2008	DBLP DOI BibTeX RDF
1	Wayne Chen, Lesley Shannon	An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs.	FPT	2008	DBLP DOI BibTeX RDF
1	Edward Chen, Dorian Sabaz, William A. Gruver, Lesley Shannon	A new flexible PR domain model to replace the fixed multi-PR region model for DPR systems.	FPT	2008	DBLP DOI BibTeX RDF
1	Patrick Lysaght	Re-visiting the challenges of programmable concurrent architectures.	FPT	2008	DBLP DOI BibTeX RDF
1	Husain Parvez, Zied Marrakchi, Umer Farooq 0001, Habib Mehrez	A new coarse-grained FPGA architecture exploration environment.	FPT	2008	DBLP DOI BibTeX RDF
1	Florent de Dinechin, Bogdan Pasca 0001, Octavian Cret, Radu Tudoran	An FPGA-specific approach to floating-point accumulation and sum-of-products.	FPT	2008	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	A scalable reconfiguration mechanism for fast dynamic reconfiguration.	FPT	2008	DBLP DOI BibTeX RDF
1	Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen	An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration.	FPT	2008	DBLP DOI BibTeX RDF
1	Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton	Optimizing coarse-grained units in floating point hybrid FPGA.	FPT	2008	DBLP DOI BibTeX RDF
1	Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner	An area-efficient FPGA realisation of a codebook-based image compression method.	FPT	2008	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung	Modelling and compensating for clock skew variability in FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Daniel Nunes, Manuel Saldaña, Paul Chow	A profiler for a heterogeneous multi-core multi-FPGA system.	FPT	2008	DBLP DOI BibTeX RDF
1	Moritz Schmid, Daniel Ziener, Jürgen Teich	Netlist-level IP protection by watermarking for LUT-based FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Wen-Kai Tsai, Zeng-Chuan Wu	Real-time FPGA architecture of extended linear convolution for digital image scaling.	FPT	2008	DBLP DOI BibTeX RDF
1	Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama	A systolic regular expression pattern matching engine and its application to network intrusion detection.	FPT	2008	DBLP DOI BibTeX RDF
1	Zong Wang, Tughrul Arslan	A low power reconfigurable heterogeneous architecture for a mobile SDR system.	FPT	2008	DBLP DOI BibTeX RDF
1	Naoto Miyamoto, Tadahiro Ohmi	Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation.	FPT	2008	DBLP DOI BibTeX RDF
1	Haohuan Fu, Oskar Mencer, Wayne Luk	Optimizing residue arithmetic on FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Huynh Phung Huynh, Tulika Mitra	Processor customization for wearable bio-monitoring platforms.	FPT	2008	DBLP DOI BibTeX RDF
1	Markos Papadonikolakis, Christos-Savvas Bouganis	A scalable FPGA architecture for non-linear SVM training.	FPT	2008	DBLP DOI BibTeX RDF
1	Yingxi Lu, Máire O'Neill, John V. McCanny	FPGA implementation and analysis of random delay insertion countermeasure against DPA.	FPT	2008	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	Estimation of sample mean and variance for Monte-Carlo simulations.	FPT	2008	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Wave-pipelined signaling for on-FPGA communication.	FPT	2008	DBLP DOI BibTeX RDF
1	Johnny Tsung Lin Ho, Guy G. F. Lemieux	PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters.	FPT	2008	DBLP DOI BibTeX RDF
1	Kentaro Sano, Takeshi Nishikawa, Takayuki Aoki, Satoru Yamamoto	Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computation.	FPT	2008	DBLP DOI BibTeX RDF
1	Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano	Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors.	FPT	2008	DBLP DOI BibTeX RDF
1	Dang Ba Khac Trieu, Tsutomu Maruyama	An implementation of a watershed algorithm based on connected components on FPGA.	FPT	2008	DBLP DOI BibTeX RDF
1	Paul Leventis	FPGA timing, power, signal integrity and other challenges at 65 and 45 nm.	FPT	2008	DBLP DOI BibTeX RDF
1	Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha (eds.)	2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008	FPT	2008	DBLP BibTeX RDF
1	Antonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan	A floating-point solver for band structured linear equations.	FPT	2008	DBLP DOI BibTeX RDF
1	Cindy Mark, Ava Shui, Steven J. E. Wilton	A system-level stochastic circuit generator for FPGA architecture evaluation.	FPT	2008	DBLP DOI BibTeX RDF
1	Shinichi Kato, Minoru Watanabe	Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI.	FPT	2008	DBLP DOI BibTeX RDF
1	Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos	Co-optimisation of datapath and memory in outer loop pipelining.	FPT	2008	DBLP DOI BibTeX RDF
1	Ni Ma, Donald G. Bailey, Christopher T. Johnston	Optimised single pass connected components analysis.	FPT	2008	DBLP DOI BibTeX RDF
1	Harold Ishebabi, Philipp Mahr, Christophe Bobda	Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs.	FPT	2008	DBLP DOI BibTeX RDF
1	Oliver Sander, Michael Hübner 0001, Jürgen Becker 0001, Matthias Traub	Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain.	FPT	2008	DBLP DOI BibTeX RDF
1	Brent Nelson	FPGA design productivity a discussion of the state of the art and a research agenda.	FPT	2008	DBLP DOI BibTeX RDF
1	Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng	Quad-level bit-stream signal processing on FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Roel Meeuws, Kamana Sigdel, Yana Yankova, Koen Bertels	High level quantitative interconnect estimation for Early Design Space Exploration.	FPT	2008	DBLP DOI BibTeX RDF
1	Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano	Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.	FPT	2008	DBLP DOI BibTeX RDF
1	Samuel J. Stone, Roy Porter, Yong C. Kim, Jason V. Paul	A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applications.	FPT	2008	DBLP DOI BibTeX RDF
1	Mihai Sima, Michael McGuire, Scott Miller	Reconfigurable array for transcendental functions calculation.	FPT	2008	DBLP DOI BibTeX RDF
1	Kazuya Tanigawa, Tetsuo Hironaka	Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation.	FPT	2008	DBLP DOI BibTeX RDF
1	Mao Nakajima, Minoru Watanabe	An 11, 424-gate dynamic optically reconfigurable gate array VLSI.	FPT	2008	DBLP DOI BibTeX RDF
1	Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	A transition probability based delay measurement method for arbitrary circuits on FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Tomás Martínek, Matej Lexa	Hardware acceleration of approximate palindromes searching.	FPT	2008	DBLP DOI BibTeX RDF
1	Philip Garcia, Katherine Compton	Kernel sharing on reconfigurable multiprocessor systems.	FPT	2008	DBLP DOI BibTeX RDF
1	Rosemary M. Francis, Simon W. Moore	Exploring hard and soft networks-on-chip for FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
1	Wenyin Fu, Katherine Compton	Balanced allocation of compute time in hardware-accelerated systems.	FPT	2008	DBLP DOI BibTeX RDF
1	Joon Edward Sim, Tulika Mitra, Weng-Fai Wong	Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architectures.	FPT	2008	DBLP DOI BibTeX RDF
1	Markus Rullmann, Renate Merker	Synthesis of efficiently reconfigurable datapaths for reconfigurable computing.	FPT	2008	DBLP DOI BibTeX RDF
1	Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik	ACS: An Addressless Configuration Support for efficient partial reconfigurations.	FPT	2008	DBLP DOI BibTeX RDF
1	Kofi Appiah, Andrew Hunter, Patrick Dickinson, Jonathan D. Owens	A run-length based connected component algorithm for FPGA implementation.	FPT	2008	DBLP DOI BibTeX RDF
1	Esam El-Araby, Preetham Nosum, Tarek A. El-Ghazawi	Productivity of High-Level Languages on Reconfigurable Computers: An HPC Perspective.	FPT	2007	DBLP DOI BibTeX RDF
1	Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert	TAS-MRAM based Non-volatile FPGA logic circuit.	FPT	2007	DBLP DOI BibTeX RDF
1	Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno	Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction.	FPT	2007	DBLP DOI BibTeX RDF
1	David P. Coggins, David W. P. Thomas, Barrie Hayes-Gill, Yiqun Zhu	An FPGA Based Travelling-Wave Fault Location System.	FPT	2007	DBLP DOI BibTeX RDF
1	Tsutomu Sasao, Hiroki Nakahara	Implementations of Reconfigurable Logic Arrays on FPGAs.	FPT	2007	DBLP DOI BibTeX RDF
1	Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi	A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip.	FPT	2007	DBLP DOI BibTeX RDF
1	Zubair Nawaz, Ozana Silvia Dragomir, Thomas Marconi, Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems.	FPT	2007	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks.	FPT	2007	DBLP DOI BibTeX RDF
1	Cameron D. Patterson, Brian S. Martin, Steven W. Ellingson, John H. Simonetti, Sean E. Cutchin	FPGA Cluster Computing in the ETA Radio Telescope.	FPT	2007	DBLP DOI BibTeX RDF
1	William Kamp, Andrew Bainbridge-Smith	Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation.	FPT	2007	DBLP DOI BibTeX RDF
1	Peter Jamieson, Jonathan Rose	Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters.	FPT	2007	DBLP DOI BibTeX RDF
1	Jacob A. Bower, Wei Ning Cho, Wayne Luk	Unifying FPGA Hardware Development.	FPT	2007	DBLP DOI BibTeX RDF

Publications at "FPT"( http://dblp.L3S.de/Venues/FPT )