Search results for "HPCA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Guangyu Sun 0003, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie 0001, Yiran Chen 0001, Hai Li 0001	A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.	HPCA	2010	DBLP DOI BibTeX RDF
1	Mingsong Bi, Igor Crk, Chris Gniady	IADVS: On-demand performance for interactive applications.	HPCA	2010	DBLP DOI BibTeX RDF
1	Libo Huang, Li Shen 0007, Zhiying Wang 0003, Wei Shi, Nong Xiao, Sheng Ma	SIF: Overcoming the limitations of SIMD devices via implicit permutation.	HPCA	2010	DBLP DOI BibTeX RDF
1	Tilak Agerwala	Exascale computing: The challenges and opportunities in the next decade.	HPCA	2010	DBLP DOI BibTeX RDF
1	Polychronis Xekalakis, Marcelo Cintra	Handling branches in TLS systems with Multi-Path Execution.	HPCA	2010	DBLP DOI BibTeX RDF
1	Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert	Explaining cache SER anomaly using DUE AVF measurement.	HPCA	2010	DBLP DOI BibTeX RDF
1	Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy	UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.	HPCA	2010	DBLP DOI BibTeX RDF
1	Mingsong Bi, Ran Duan, Chris Gniady	Delay-Hiding energy management mechanisms for DRAM.	HPCA	2010	DBLP DOI BibTeX RDF
1	Yan Pan, John Kim, Gokhan Memik	FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar.	HPCA	2010	DBLP DOI BibTeX RDF
1	Xiaowei Jiang, Niti Madan, Li Zhao 0002, Mike Upton, Ravishankar R. Iyer 0001, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian	CHOP: Adaptive filter-based DRAM caching for CMP server platforms.	HPCA	2010	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño	Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing.	HPCA	2010	DBLP DOI BibTeX RDF
1	Tong Li 0003, Paul Brett, Rob C. Knauerhase, David A. Koufaty, Dheeraj Reddy, Scott Hahn	Operating system support for overlapping-ISA heterogeneous multi-core architectures.	HPCA	2010	DBLP DOI BibTeX RDF
1	Sajib Kundu, Raju Rangaswami, Kaushik Dutta, Ming Zhao 0002	Application performance modeling in a virtualized environment.	HPCA	2010	DBLP DOI BibTeX RDF
1	Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter	ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.	HPCA	2010	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian	Towards scalable, energy-efficient, bus-based on-chip networks.	HPCA	2010	DBLP DOI BibTeX RDF
1	Andrew D. Hilton, Amir Roth	BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution.	HPCA	2010	DBLP DOI BibTeX RDF
1	Syed Ali Raza Jafri, Mithuna Thottethodi, T. N. Vijaykumar	LiteTM: Reducing transactional state overhead.	HPCA	2010	DBLP DOI BibTeX RDF
1	Yaozu Dong, Xiaowei Yang, Xiaoyong Li, Jianhui Li, Kun Tian, Haibing Guan	High performance network virtualization with SR-IOV.	HPCA	2010	DBLP DOI BibTeX RDF
1	Arvind	Is hardware innovation over?	HPCA	2010	DBLP DOI BibTeX RDF
1	Matthew T. Jacob, Chita R. Das, Pradip Bose (eds.)	16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 9-14 January 2010, Bangalore, India	HPCA	2010	DBLP BibTeX RDF
1	Jaume Abella 0001, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González 0001	High-Performance low-vcc in-order core.	HPCA	2010	DBLP DOI BibTeX RDF
1	Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald III, Nathan Beckmann, Christopher Celio, Jonathan Eastep, Anant Agarwal	Graphite: A distributed parallel simulator for multicores.	HPCA	2010	DBLP DOI BibTeX RDF
1	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
1	Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles	Blueshift: Designing processors for timing speculation from the ground up.	HPCA	2009	DBLP DOI BibTeX RDF
1	Sebastian Herbert, Diana Marculescu	Variation-aware dynamic voltage/frequency scaling.	HPCA	2009	DBLP DOI BibTeX RDF
1	Parthasarathy Ranganathan	Industrial perspectives panel.	HPCA	2009	DBLP DOI BibTeX RDF
1	Amit Kumar 0008, Ram Huggahalli, Srihari Makineni	Characterization of Direct Cache Access on multi-core systems and 10GbE.	HPCA	2009	DBLP DOI BibTeX RDF
1	Lide Duan, Bin Li 0008, Lu Peng 0001	Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics.	HPCA	2009	DBLP DOI BibTeX RDF
1	Xi E. Chen, Tor M. Aamodt	A first-order fine-grained multithreaded throughput model.	HPCA	2009	DBLP DOI BibTeX RDF
1	Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou	Hardware-software integrated approaches to defend against software cache-based side channel attacks.	HPCA	2009	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Onur Mutlu, Yale N. Patt	Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems.	HPCA	2009	DBLP DOI BibTeX RDF
1	Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh	Criticality-based optimizations for efficient load processing.	HPCA	2009	DBLP DOI BibTeX RDF
1	Ibrahim Hur, Calvin Lin	Feedback mechanisms for improving probabilistic memory prefetching.	HPCA	2009	DBLP DOI BibTeX RDF
1	Vilas Sridharan, David R. Kaeli	Eliminating microarchitectural dependency from Architectural Vulnerability.	HPCA	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	Multi-core demands multi-interfaces.	HPCA	2009	DBLP DOI BibTeX RDF
1	Mark D. Hill	Opportunities beyond single-core microprocessors.	HPCA	2009	DBLP DOI BibTeX RDF
1	Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter	Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.	HPCA	2009	DBLP DOI BibTeX RDF
1	Prith Banerjee	An intelligent IT infrastructure for the future.	HPCA	2009	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction router: Yet another low latency on-chip router architecture.	HPCA	2009	DBLP DOI BibTeX RDF
1	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
1	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Practical off-chip meta-data for temporal memory streaming.	HPCA	2009	DBLP DOI BibTeX RDF
1		15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA	HPCA	2009	DBLP BibTeX RDF
1	Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam	Reconciling specialization and flexibility through compound circuits.	HPCA	2009	DBLP DOI BibTeX RDF
1	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.	HPCA	2009	DBLP DOI BibTeX RDF
1	Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu	Express Cube Topologies for on-Chip Interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith 0001, David M. Brooks	Voltage emergency prediction: Using signatures to reduce operating margins.	HPCA	2009	DBLP DOI BibTeX RDF
1	Niti Madan, Li Zhao 0002, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer 0001, Srihari Makineni, Donald Newell	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	HPCA	2009	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi	Adaptive Spill-Receive for robust high-performance caching in CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	George Michelogiannakis, James D. Balfour, William J. Dally	Elastic-buffer flow control for on-chip networks.	HPCA	2009	DBLP DOI BibTeX RDF
1	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
1	Mainak Chaudhuri	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.	HPCA	2009	DBLP DOI BibTeX RDF
1	Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve	Accurate microarchitecture-level fault modeling for studying hardware faults.	HPCA	2009	DBLP DOI BibTeX RDF
1	Mark Stephenson, Lixin Zhang 0002, Ram Rangan	Lightweight predication support for out of order processors.	HPCA	2009	DBLP DOI BibTeX RDF
1	Andrew D. Hilton, Santosh Nagarakatte, Amir Roth	iCFP: Tolerating all-level cache misses in in-order processors.	HPCA	2009	DBLP DOI BibTeX RDF
1	Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen 0002, Haihua Shen, Pengyu Wang, Hong Pan	Fast complete memory consistency verification.	HPCA	2009	DBLP DOI BibTeX RDF
1	Yi Xu, Yu Du, Bo Zhao 0007, Xiuyi Zhou, Youtao Zhang, Jun Yang 0002	A low-radix and low-diameter 3D interconnection network design.	HPCA	2009	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Hashem Hashemi Najaf-abadi, Eric Rotenberg	Architectural Contesting.	HPCA	2009	DBLP DOI BibTeX RDF
1	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Sangmin Seo, Jaejin Lee, Zehra Sura	Design and implementation of software-managed caches for multicores with local memory.	HPCA	2009	DBLP DOI BibTeX RDF
1	Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, Ciji Isen	Automated microprocessor stressmark generation.	HPCA	2008	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh	PEEP: Exploiting predictability of memory dependences in SMT processors.	HPCA	2008	DBLP DOI BibTeX RDF
1	Paul Gratz, Boris Grot, Stephen W. Keckler	Regional congestion awareness for load balance in networks-on-chip.	HPCA	2008	DBLP DOI BibTeX RDF
1	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF
1	Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin	Single-level integrity and confidentiality protection for distributed shared memory multiprocessors.	HPCA	2008	DBLP DOI BibTeX RDF
1	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
1	Luiz E. Ramos, Ricardo Bianchini	C-Oracle: Predictive thermal management for data centers.	HPCA	2008	DBLP DOI BibTeX RDF
1	M. Wasiur Rashid, Michael C. Huang 0001	Supporting highly-decoupled thread-level redundancy for parallel programs.	HPCA	2008	DBLP DOI BibTeX RDF
1	Benjamin C. Lee, David M. Brooks	Roughness of microarchitectural design topologies and its implications for optimization.	HPCA	2008	DBLP DOI BibTeX RDF
1	Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic	FlexiTaint: A programmable accelerator for dynamic taint propagation.	HPCA	2008	DBLP DOI BibTeX RDF
1	Kevin Leigh, Parthasarathy Ranganathan, Jaspal Subhlok	Fabric convergence implications on systems architecture.	HPCA	2008	DBLP DOI BibTeX RDF
1	Joe Rattner	Intel's Tera-scale Computing Project: The first five years, the next five years.	HPCA	2008	DBLP DOI BibTeX RDF
1	Christian Fensch, Marcelo Cintra	An OS-based alternative to full hardware coherence on tiled CMPs.	HPCA	2008	DBLP DOI BibTeX RDF
1	Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang 0010, Xiaodong Zhang 0001, P. Sadayappan	Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems.	HPCA	2008	DBLP DOI BibTeX RDF
1	Qian Diao, Justin J. Song	Prediction of CPU idle-busy activity pattern.	HPCA	2008	DBLP DOI BibTeX RDF
1	Kaiyu Chen, Sharad Malik, Priyadarsan Patra	Runtime validation of memory ordering using constraint graph checking.	HPCA	2008	DBLP DOI BibTeX RDF
1	Frances E. Allen	Compilers and parallel computing systems.	HPCA	2008	DBLP DOI BibTeX RDF
1	Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David M. Brooks	System level analysis of fast, per-core DVFS using on-chip switching regulators.	HPCA	2008	DBLP DOI BibTeX RDF
1	Pierre Salverda, Craig B. Zilles	Fundamental performance constraints in horizontal fusion of in-order cores.	HPCA	2008	DBLP DOI BibTeX RDF
1		14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA	HPCA	2008	DBLP BibTeX RDF
1	Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith 0001, Gu-Yeon Wei, David M. Brooks	DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.	HPCA	2008	DBLP DOI BibTeX RDF
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads to improve SMT performance.	HPCA	2008	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Performance-aware speculation control using wrong path usefulness prediction.	HPCA	2008	DBLP DOI BibTeX RDF
1	Richard H. Larson, John K. Salmon, Ron O. Dror, Martin M. Deneroff, Cliff Young, J. P. Grossman, Yibing Shan, John L. Klepeis, David E. Shaw	High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation.	HPCA	2008	DBLP DOI BibTeX RDF
1	Luis Useche, Jorge Guerra, Medha Bhadkamkar, Mauricio Alarcon, Raju Rangaswami	EXCES: External caching in energy saving storage systems.	HPCA	2008	DBLP DOI BibTeX RDF
1	Xiaorui Wang, Ming Chen 0002	Cluster-level feedback power control for performance optimization.	HPCA	2008	DBLP DOI BibTeX RDF
1	Sumeet Kumar, Aneesh Aggarwal	Speculative instruction validation for performance-reliability trade-off.	HPCA	2008	DBLP DOI BibTeX RDF
1	JaeWoong Chung, Michael Dalton, Hari Kannan, Christos Kozyrakis	Thread-safe dynamic binary translation using transactional memory.	HPCA	2008	DBLP DOI BibTeX RDF
1	M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam	CMP network-on-chip overlaid with multi-band RF-interconnect.	HPCA	2008	DBLP DOI BibTeX RDF
1	Mark D. Hill	Amdahl's Law in the multicore era.	HPCA	2008	DBLP DOI BibTeX RDF
1	Jeffrey Kuskin, Cliff Young, J. P. Grossman, Brannon Batson, Martin M. Deneroff, Ron O. Dror, David E. Shaw	Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation.	HPCA	2008	DBLP DOI BibTeX RDF
1	Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank	Branch-mispredict level parallelism (BLP) for control independence.	HPCA	2008	DBLP DOI BibTeX RDF
1	Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthew I. Frank	PaCo: Probability-based path confidence prediction.	HPCA	2008	DBLP DOI BibTeX RDF
1	Valentina Salapura, Matthias A. Blumrich, Alan Gara	Design and implementation of the blue gene/P snoop filter.	HPCA	2008	DBLP DOI BibTeX RDF
1	Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou	Address-branch correlation: A novel locality for long-latency hard-to-predict branches.	HPCA	2008	DBLP DOI BibTeX RDF
1	Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberman, Scott A. Mahlke	Uncovering hidden loop level parallelism in sequential applications.	HPCA	2008	DBLP DOI BibTeX RDF
1	Philip M. Wells, Gurindar S. Sohi	Serializing instructions in system-intensive workloads: Amdahl's Law strikes again.	HPCA	2008	DBLP DOI BibTeX RDF
1	Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith 0001	Power-Efficient DRAM Speculation.	HPCA	2008	DBLP DOI BibTeX RDF

Publications at "HPCA"( http://dblp.L3S.de/Venues/HPCA )