Search results for "ISPD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kusnadi, Jo Dale Carothers	A method of measuring nets routability for MCM's general area routing problems.	ISPD	1999	DBLP DOI BibTeX RDF
1	Dirk Stroobandt, Peter Verplaetse, Jan Van Campenhout	Towards synthetic benchmark circuits for evaluating timing-driven CAD tools.	ISPD	1999	DBLP DOI BibTeX RDF
1	Kevin T. Tang, Eby G. Friedman	Interconnect coupling noise in CMOS VLSI circuits.	ISPD	1999	DBLP DOI BibTeX RDF
1	Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky	Optimal phase conflict removal for layout of dark field alternating phase shifting masks.	ISPD	1999	DBLP DOI BibTeX RDF
1	Yanhong Yuan, Prithviraj Banerjee	Incremental capacitance extraction and its application to iterative timing-driven detailed routing.	ISPD	1999	DBLP DOI BibTeX RDF
1	Wei Chen, Cheng-Ta Hsieh, Massoud Pedram	Gate sizing with controlled displacement.	ISPD	1999	DBLP DOI BibTeX RDF
1	Joseph L. Ganley	Efficient solution of systems of orientation constraints.	ISPD	1999	DBLP DOI BibTeX RDF
1	Sung-Woo Hur, Ashok Jagannathan, John Lillis	Timing driven maze routing.	ISPD	1999	DBLP DOI BibTeX RDF
1	Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi	A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design.	ISPD	1999	DBLP DOI BibTeX RDF
1	Ching-Han Tsai, Sung-Mo Kang	Standard cell placement for even on-chip thermal distribution.	ISPD	1999	DBLP DOI BibTeX RDF
1	Sachio Hayashi, Masaaki Yamada	EMI-noise analysis under ASIC design environment.	ISPD	1999	DBLP DOI BibTeX RDF
1	Michael A. Riepe, Karem A. Sakallah	Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis.	ISPD	1999	DBLP DOI BibTeX RDF
1	Patrick H. Madden	Partitioning by iterative deletion.	ISPD	1999	DBLP DOI BibTeX RDF
1	Jiang Hu, Sachin S. Sapatnekar	Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.	ISPD	1999	DBLP DOI BibTeX RDF
1	Durgam Vahia, Maciej J. Ciesielski	Transistor level placement for full custom datapath cell design.	ISPD	1999	DBLP DOI BibTeX RDF
1	D. F. Wong 0001 (eds.)	Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999	ISPD	1999	DBLP DOI BibTeX RDF
1	Xuan Zeng 0001, Dian Zhou, Wei Li	Buffer insertion for clock delay and skew minimization.	ISPD	1999	DBLP DOI BibTeX RDF
1	Ralph H. J. M. Otten	Global wires: harmful?.	ISPD	1998	DBLP DOI BibTeX RDF
1	Majid Sarrafzadeh (eds.)	Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998	ISPD	1998	DBLP DOI BibTeX RDF
1	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky	On wirelength estimations for row-based placement.	ISPD	1998	DBLP DOI BibTeX RDF
1	Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas	A pattern matching algorithm for verification and analysis of very large IC layouts.	ISPD	1998	DBLP DOI BibTeX RDF
1	Huibo Hou, Sachin S. Sapatnekar	Routing tree topology construction to meet interconnect timing constraints.	ISPD	1998	DBLP DOI BibTeX RDF
1	Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl	Analysis, reduction and avoidance of crosstalk on VLSI chips.	ISPD	1998	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, D. F. Wong 0001	Greedy wire-sizing is linear time.	ISPD	1998	DBLP DOI BibTeX RDF
1	Andrew B. Kahng	Futures for partitioning in physical design (tutorial).	ISPD	1998	DBLP DOI BibTeX RDF
1	S. DasGupta	Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel).	ISPD	1998	DBLP DOI BibTeX RDF
1	S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, Amrich Chokhavtia	CHDStd - application support for reusable hierarchical interconnect timing views.	ISPD	1998	DBLP DOI BibTeX RDF
1	Evanthia Papadopoulou, D. T. Lee	Critical area computation - a new approach.	ISPD	1998	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Sudhakar Muddu	New efficient algorithms for computing effective capacitance.	ISPD	1998	DBLP DOI BibTeX RDF
1	Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen	Chip-level area routing.	ISPD	1998	DBLP DOI BibTeX RDF
1	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	ISPD	1998	DBLP DOI BibTeX RDF
1	Charles J. Alpert	The ISPD98 circuit benchmark suite.	ISPD	1998	DBLP DOI BibTeX RDF
1	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy.	ISPD	1998	DBLP DOI BibTeX RDF
1	Sudhakar Bobba, Ibrahim N. Hajj	Estimation of maximum current envelope for power bus analysis and design.	ISPD	1998	DBLP DOI BibTeX RDF
1	Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng	LIBRA - a library-independent framework for post-layout performance optimization.	ISPD	1998	DBLP DOI BibTeX RDF
1	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
1	Lawrence T. Pileggi	Timing metrics for physical design of deep submicron technologies.	ISPD	1998	DBLP DOI BibTeX RDF
1	Temo Chen, Michael K. H. Fan	On convex formulation of the floorplan area minimization problem.	ISPD	1998	DBLP DOI BibTeX RDF
1	Hiroshi Murata, Ernest S. Kuh	Sequence-pair based placement method for hard/soft/pre-placed modules.	ISPD	1998	DBLP DOI BibTeX RDF
1	Shantanu Dutt, Halim Theny	Partitioning using second-order information and stochastic-gain functions.	ISPD	1998	DBLP DOI BibTeX RDF
1	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain design.	ISPD	1998	DBLP DOI BibTeX RDF
1	Guang-Ming Wu, Yao-Wen Chang	Switch-matrix architecture and routing for FPDs.	ISPD	1998	DBLP DOI BibTeX RDF
1	Payam Heydari, Massoud Pedram	Calculation of ramp response of lossy transmission lines using two-port network functions.	ISPD	1998	DBLP DOI BibTeX RDF
1	Akira Nagao, Takashi Kambe, Isao Shirakawa	A layout approach to monolithic microwave IC.	ISPD	1998	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky	Filling and slotting: analysis and algorithms.	ISPD	1998	DBLP DOI BibTeX RDF
1	Maggie Zhiwei Kang, Wayne Wei-Ming Dai	Topology constrained rectilinear block packing for layout reuse.	ISPD	1998	DBLP DOI BibTeX RDF
1	Wojciech Maly	Moore's law and physical design of ICs.	ISPD	1998	DBLP DOI BibTeX RDF
1	Jason Cong, Lei He 0001	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
1	Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng	Rectilinear block placement using sequence-pair.	ISPD	1998	DBLP DOI BibTeX RDF
1	Huiqun Liu, D. F. Wong 0001	Network flow based multi-way partitioning with area and pin constraints.	ISPD	1997	DBLP DOI BibTeX RDF
1	Parthasarathi Dasgupta, Susmita Sur-Kolay	Slicibility of rectangular graphs and floorplan optimization.	ISPD	1997	DBLP DOI BibTeX RDF	graph dualization, nonslicible floorplans, slicible floorplans, very large scale integration, heuristic search, planar graphs, floorplanning
1	Nevin Kapur, Debabrata Ghosh, Franc Brglez	Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.	ISPD	1997	DBLP DOI BibTeX RDF
1	Dennis J.-H. Huang, Andrew B. Kahng	Partitioning-based standard-cell global placement with an exact objective.	ISPD	1997	DBLP DOI BibTeX RDF
1	Jason Cong, Patrick H. Madden	Performance driven global routing for standard cell design.	ISPD	1997	DBLP DOI BibTeX RDF
1	Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic	On two-step routing for FPGAS.	ISPD	1997	DBLP DOI BibTeX RDF
1	Michael J. Alexander	Power optimization for FPGA look-up tables.	ISPD	1997	DBLP DOI BibTeX RDF
1	Jun Dong Cho	A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction.	ISPD	1997	DBLP DOI BibTeX RDF
1	Dian Zhou, Xingya Liu	Minimization of chip size and power consumption of high-speed VLSI buffers.	ISPD	1997	DBLP DOI BibTeX RDF
1	A. Bertolet, K. Carpenter, Keith M. Carrig, Albert M. Chu, A. Dean, Frank D. Ferraiolo, Stephan Kenyon, D. Phan, John G. Petrovick, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. Andrew Scott, Richard J. Weiss	A pseudo-hierarchical methodology for high performance microprocessor design.	ISPD	1997	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, D. F. Wong 0001	Closed form solution to simultaneous buffer insertion/sizing and wire sizing.	ISPD	1997	DBLP DOI BibTeX RDF
1	Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko	VLSI/PCB placement with obstacles based on sequence-pair.	ISPD	1997	DBLP DOI BibTeX RDF
1	Fung Yu Young, D. F. Wong 0001	How good are slicing floorplans?.	ISPD	1997	DBLP DOI BibTeX RDF
1	R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele	Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.	ISPD	1997	DBLP DOI BibTeX RDF
1	Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar	Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.	ISPD	1997	DBLP DOI BibTeX RDF
1	Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin	Preserving HDL synthesis hierarchy for cell placement.	ISPD	1997	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Majid Sarrafzadeh (eds.)	Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997	ISPD	1997	DBLP DOI BibTeX RDF
1	Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy	The future of logic synthesis and physical design in deep-submicron process geometries.	ISPD	1997	DBLP DOI BibTeX RDF
1	Glenn Holt, Akhilesh Tyagi	Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis.	ISPD	1997	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan	Faster minimization of linear wirelength for global placement.	ISPD	1997	DBLP DOI BibTeX RDF
1	T. C. Hu	Physical design: mathematical models and methods.	ISPD	1997	DBLP DOI BibTeX RDF
1	Young-Jun Cha, Chong S. Rim, Kazuo Nakajima	A simple and effective greedy multilayer router for MCMs.	ISPD	1997	DBLP DOI BibTeX RDF
1	Ernest S. Kuh	Physical design: reminiscing and looking ahead.	ISPD	1997	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, D. F. Wong 0001	A matrix synthesis approach to thermal placement.	ISPD	1997	DBLP DOI BibTeX RDF
1	R. X. T. Nijssen, C. A. J. van Eijk	Regular layout generation of logically optimized datapaths.	ISPD	1997	DBLP DOI BibTeX RDF
1	Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez	A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation.	ISPD	1997	DBLP DOI BibTeX RDF
1	Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi	EWA: exact wiring-sizing algorithm.	ISPD	1997	DBLP DOI BibTeX RDF
1	Jason Cong, Andrew B. Kahng, Kwok-Shing Leung	Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.	ISPD	1997	DBLP DOI BibTeX RDF
1	Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes	Timing driven placement in interaction with netlist transformations.	ISPD	1997	DBLP DOI BibTeX RDF
1	C. Douglass Bateman, Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky	Provably good routing tree construction with multi-port terminals.	ISPD	1997	DBLP DOI BibTeX RDF
1	Raul Camposano	The quarter micron challenge: intergrating physical and logic design.	ISPD	1997	DBLP DOI BibTeX RDF
1	David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif	Physical design challenges for performance.	ISPD	1997	DBLP DOI BibTeX RDF
1	Jeffrey L. Burns, Jack A. Feldman	C5M - a control logic layout synthesis system for high-performance microprocessors.	ISPD	1997	DBLP DOI BibTeX RDF
1	Louis Scheffer	A roadmap of CAD tool changes for sub-micron interconnect problems.	ISPD	1997	DBLP DOI BibTeX RDF

Publications at "ISPD"( http://dblp.L3S.de/Venues/ISPD )