Search results for "ISVLSI"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Raluca Marinescu, Eduard Paul Enoiu, Cristina Seceleanu	Statistical Analysis of Resource Usage of Embedded Systems Modeled in EAST-ADL.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Saha Mousumi, Biplab K. Sikdar	A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache Module.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Shital Joshi, Elias Kougianos, Saraju P. Mohanty	Simscape Based Ultra-Fast Design Exploration of Graphene-Nanoelectronic Systems.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Jérôme Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi	Digital Right Management for IP Protection.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Moon Seok Kim, William Cane-Wissing, Jack Sampson, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta	Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli	Exploiting Circuit Duality to Speed up SAT.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Kaushik Roy 0001, Anand Raghunathan	Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	M. E. Portnoi, V. A. Saroka, R. R. Hartmann, O. V. Kibis	Terahertz Applications of Carbon Nanotubes and Graphene Nanoribbons.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Christian Piguet, Marc Pons 0001, Daniel Séverac	Sub-Threshold Design and Architectural Choices.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Masoud Oveis Gharan, Gul N. Khan	Index-Based Round-Robin Arbiter for NoC Routers.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard	Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Shweta Malik, Georg T. Becker, Christof Paar, Wayne P. Burleson	Development of a Layout-Level Hardware Obfuscation Tool.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Kaisheng Ma, Nandhini Chandramoorthy, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan	Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Jiafan Wang 0002, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu	Built-In Self Optimization for Variation Resilience of Analog Filters.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Yannick Bornat, Adam Quotb, Noëlle Lewis, Sylvie Renaud	Resource Optimized Processor for Real-Time Neural Activity Monitoring.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel	A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Soumyadip Bandyopadhyay, Dipankar Sarkar 0001, Chittaranjan A. Mandal	Validating SPARK: High Level Synthesis Compiler.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Ahmedullah Aziz, William Cane-Wissing, Moon Seok Kim, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta	Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Edward Jung, Seonho Choi	Identification of IP Control Units by State Encoding.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Rajshekar Kalayappan, Smruti R. Sarangi	SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra	A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal	A New Method for Defining Monotone Staircases in VLSI Floorplans.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Christian Brugger, Valentin Grigorovici, Matthias Jung 0001, Christian Weis, Christian de Schryver, Katharina Anna Zweig, Norbert Wehn	A Custom Computing System for Finding Similarties in Complex Networks.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir	Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy	Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Giuseppe Airo Farulla, Ludovico Orlando Russo, Vincenzo Gallifuoco, Marco Indaco	A Novel Architectural Pattern to Support the Development of Human-Robot Interaction (HRI) Systems Integrating Haptic Interfaces and Gesture Recognition Algorithms.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Arathi Ajay, R. Mary Lourde	VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Hao Liu, Clement Devigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner	RWT: Suppressing Write-Through Cost When Coherence is Not Needed.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Olivier Rossel, Fabien Soulier, Serge Bernard, David Guiraud, Guy Cathébras	In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Elena Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto	STT-MRAM-Based Strong PUF Architecture.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Jeremy Schlachter, Vincent Camus, Christian C. Enz	Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Kunal Banerjee 0001, Chittaranjan A. Mandal, Dipankar Sarkar 0001	Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Anderson Luiz Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Gusmão de Lima Kastensmidt, Stephan Wong, Antonio Carlos Schneider Beck	A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Brice Colombier, Lilian Bossuet, David Hély	Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Jérémie Clément, Bruno Mussard, David Naccache, Lionel Torres	Implementation of AES Using NVM Memories Based on Comparison Function.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler	Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Elena K. Weinberg, Mircea R. Stan	SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Diagnosis of Delay Faults Considering Hazards.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat	A Detailed Routing-Aware Detailed Placement Technique.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Yan Fang, Victor V. Yashin, Donald M. Chiarulli, Steven P. Levitan	A Simplified Phase Model for Oscillator Based Computing.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Ali Ibrahim, Maurizio Valle, Luca Noli, Hussein Chible	Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value Decomposition.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell	A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Daijiro Murooka, Yu Zhang, Qing Dong 0002, Shigetoshi Nakatake	Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero	Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Zhen Li 0046, Sébastien Le Beux, Christelle Monat, Xavier Letartre, Ian O'Connor	Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Anastasiia Butko, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert	Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.	ISVLSI	2015	DBLP DOI BibTeX RDF
1	Lin Liu 0013, Yuchen Zhou, Shiyan Hu	Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Vipul Kumar Mishra	Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Karim Kanoun, Martino Ruggiero, David Atienza, Mihaela van der Schaar	Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi	Function Extraction from Arithmetic Bit-Level Circuits.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Kaisheng Ma, Huichu Liu, Yang Xiao 0002, Yang Zheng, Xueqing Li, Sumeet Kumar Gupta, Yuan Xie 0001, Vijaykrishnan Narayanan	Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Garrett Steven Rose	A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh	A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel	2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi	Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Apostolos Dollas	Big Data Processing with FPGA Supercomputers: Opportunities and Challenges.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Yue Wang, Nagarajan Ranganathan	A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Hai Li 0001, Miao Hu, Chuandong Li 0001, Shukai Duan	Memristor Modeling - Static, Statistical, and Stochastic Methodologies.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Zhe Wang 0003, Weichen Liu, Jiang Xu 0001, Bin Li 0018, Ravi R. Iyer 0001, Ramesh Illikkal, Xiaowen Wu, Wai Ho Mow, Wenjing Ye	A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Debashri Roy, Prasun Ghosal, Saraju P. Mohanty	FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Jungmin Park, Akhilesh Tyagi	Towards Making Private Circuits Practical: DPA Resistant Private Circuits.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson	Post-Silicon Validation and Calibration of Hardware Security Primitives.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	André Luiz Pereira de França, Ricardo Pereira Jasinski, Volnei Antonio Pedroni, Altair Olivo Santin	Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier	A Broadcast-Enabled Sensing System for Embedded Multi-core Processors.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao 0001	Where is the Achilles Heel under Circuit Aging.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Cory E. Merkel, Dhireesha Kudithipudi	Neuromemristive Extreme Learning Machines for Pattern Classification.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Ke Jiang, Lejla Batina, Petru Eles, Zebo Peng	Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad	Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Mahanama Wickramasinghe, Hui Guo 0001	Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Zheng Wang 0020, Goutam Paul 0001, Anupam Chattopadhyay	Processor Design with Asymmetric Reliability.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Jun Zhou 0022, Huawei Li 0001, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li 0001	HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Juan Yi, Weichen Liu, Weiwen Jiang, Mingwen Qin, Lei Yang 0018, Duo Liu, Chunming Xiao, Luelue Du, Edwin Hsing-Mean Sha	An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Prateek Thakyal, Prabhat Mishra 0001	Layout-Aware Selection of Trace Signals for Post-Silicon Debug.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Mike Borowczak, Ranga Vemuri	Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Hemanta Kumar Mondal, Gade Narayana Sri Harsha, Sujay Deb	An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Tosiron Adegbija, Ann Gordon-Ross	Dynamic Phase-Based Optimization of Embedded Systems.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Liang Men, Brent Hollosi, Jia Di	Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Atul Kumar Nishad, Aditya Dalakoti, Ashish Jindal, Rahul Kumar, Somesh Kumar, Rohit Sharma	Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Vinitha Arakkonam Palaniveloo, Jude Angelo Ambrose, Arcot Sowmya	Improving GA-Based NoC Mapping Algorithms Using a Formal Model.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	K. M. Mohsin, Ashok Srivastava, Ashwani K. Sharma, Clay Mayberry	Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Lei Xu 0012, Weidong Shi	Removing the Root of Trust: Secure Oblivious Key Establishment for FPGAs.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Umamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi 0001	"Green" On-chip Inductors in Three-Dimensional Integrated Circuits.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Adriel Mota Ziesemer, Ricardo Augusto da Luz Reis	Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Vikram B. Suresh, Wayne P. Burleson	Variation Aware Design of Post-Silicon Tunable Clock Buffer.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Rupali Mitra, Debesh K. Das, Bhargab B. Bhattacharya	On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Xueqing Li, Wei-Yu Tsai, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan	A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Kaushik Roy 0001, Mrigank Sharad, Deliang Fan, Karthik Yogendra	Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Irith Pomeranz	FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Bradley T. Kiddie, William H. Robinson	Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Can Sitik, Leo Filippini, Emre Salman, Baris Taskin	High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Dominik Auras, Rainer Leupers, Gerd Ascheid	A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Hourieh Attarzadeh, Trond Ytterdal	A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman 0001, Chandan Giri	Session Based Core Test Scheduling for 3D SOCs.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul	Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.	ISVLSI	2014	DBLP DOI BibTeX RDF
1	Sophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard	Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture.	ISVLSI	2014	DBLP DOI BibTeX RDF

Publications at "ISVLSI"( http://dblp.L3S.de/Venues/ISVLSI )