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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 84 occurrences of 72 keywords
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Results
Found 927 publication records. Showing 927 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Claudia Kretzschmar, Robert Siegmund, Dietmar Müller 0001 |
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.  |
PATMOS  |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev |
Semi-modular Latch Chains for Asynchronous Circuit Design. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Vassilis Paliouras, Thanos Stouraitis |
Logarithmic Number System for Low-Power Arithmetic. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel |
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Henrik Eriksson, Per Larsson-Edefors |
Impact of Voltage Scaling on Glitch Power Consumption. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne |
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Joohee Kim, Marios C. Papaefthymiou |
Dynamic Memory Design for Low Data-Retention Power. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon |
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Raúl Jiménez, Antonio J. Acosta 0001, Eduardo J. Peralías, Adoración Rueda |
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino |
Power Models for Semi-autonomous RTL Macros. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.) |
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo |
RTL Estimation of Steering Logic Power. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante |
Early Power Estimation for System-on-Chip Designs. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel |
Power Macro-Modelling for Firm-Macro. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta 0001, Manuel Valencia-Barrero |
Degradation Delay Model Extension to CMOS Gates. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne |
Second Generation Delay Model for Submicron CMOS Process. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Achim Freimann |
Framework for High-Level Power Estimation of Signal Processing Architectures. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Tim Wichmann, Manfred Thole |
Computer Aided Generation of Analytic Models for Nonlinear Function Blocks. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Santanu Dutta |
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam |
A Holistic Approach to System Level Energy Optimization. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis |
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Francesco Pessolano, Joep L. W. Kessels |
Asynchronous First-in First-out Queues. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Reiner W. Hartenstein, Thomas Hoffmann 0001, Ulrich Nageldinger |
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonio J. Acosta 0001, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero |
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis |
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
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Displaying result #901 - #927 of 927 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10] |
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