Search results for "VTS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Irith Pomeranz, Sudhakar M. Reddy	Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.	VTS	2007	DBLP DOI BibTeX RDF
1	Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara	TAM Design and Optimization for Transparency-Based SoC Test.	VTS	2007	DBLP DOI BibTeX RDF	TAM design, transparency, ILP, SoC test
1	Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee	Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors.	VTS	2007	DBLP DOI BibTeX RDF
1	Bram Kruseman, Ananta K. Majhi, Guido Gronthoud	On Performance Testing with Path Delay Patterns.	VTS	2007	DBLP DOI BibTeX RDF
1	Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor 0001, Mike Degregorio, Steven F. Oakland	An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.	VTS	2007	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi	A UML Based System Level Failure Rate Assessment Technique for SoC Designs.	VTS	2007	DBLP DOI BibTeX RDF
1	Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou	Handling Pattern-Dependent Delay Faults in Diagnosis.	VTS	2007	DBLP DOI BibTeX RDF
1	Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee	Enhanced Resolution Jitter Testing Using Jitter Expansion.	VTS	2007	DBLP DOI BibTeX RDF
1	Marcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin	RF Digital Signal Generation Beyond Nyquist.	VTS	2007	DBLP DOI BibTeX RDF
1	Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.	VTS	2007	DBLP DOI BibTeX RDF
1	Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris	Non-RF to RF Test Correlation Using Learning Machines: A Case Study.	VTS	2007	DBLP DOI BibTeX RDF
1	Richard Putman, Nur A. Touba	Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression.	VTS	2007	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Accelerating Diagnosis via Dominance Relations between Sets of Faults.	VTS	2007	DBLP DOI BibTeX RDF
1	Kyoung Youn Cho, Edward J. McCluskey	Test Set Reordering Using the Gate Exhaustive Test Metric.	VTS	2007	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
1	Anshuman Chandra, Haihua Yan, Rohit Kapur	Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.	VTS	2007	DBLP DOI BibTeX RDF
1	Erkan Acar, Sule Ozev, Kevin B. Redmond	A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up.	VTS	2007	DBLP DOI BibTeX RDF
1	Amit Laknaur, Rui Xiao, Haibo Wang 0005	A Programmable Window Comparator for Analog Online Testing.	VTS	2007	DBLP DOI BibTeX RDF
1	Rajarajan Senguttuvan, Abhijit Chatterjee	Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection.	VTS	2007	DBLP DOI BibTeX RDF
1		25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA	VTS	2007	DBLP BibTeX RDF
1	Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	High Level Synthesis of Degradable ASICs Using Virtual Binding.	VTS	2007	DBLP DOI BibTeX RDF
1	Cecilia Metra, Martin Omaña 0001, T. M. Mak, Simon Tam 0001	Novel Approach to Clock Fault Testing for High Performance Microprocessors.	VTS	2007	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Lei Fang	RTL Test Point Insertion to Reduce Delay Test Volume.	VTS	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.	VTS	2007	DBLP DOI BibTeX RDF	scan-based DFT, security, detection probability, low overhead, cryptographic hardware
1	Jennifer Dworak	An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting.	VTS	2007	DBLP DOI BibTeX RDF
1	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra	Circuit Failure Prediction and Its Application to Transistor Aging.	VTS	2007	DBLP DOI BibTeX RDF
1	Jian Kang, Sharad C. Seth, Vijay Gangaram	Efficient RTL Coverage Metric for Functional Test Selection.	VTS	2007	DBLP DOI BibTeX RDF
1	Avijit Dutta, Nur A. Touba	Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.	VTS	2007	DBLP DOI BibTeX RDF
1	Matthieu Tuna, Mounir Benabdenbi, Alain Greiner	At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.	VTS	2007	DBLP DOI BibTeX RDF
1	Yen-Chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu	A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications.	VTS	2007	DBLP DOI BibTeX RDF
1	Claude Thibeault	On a New Outlier Rejection Technique.	VTS	2007	DBLP DOI BibTeX RDF	Multi-parameter testing, current testing
1	Soumitra Bose, Vishwani D. Agrawal	Delay Test Quality Evaluation Using Bounded Gate Delays.	VTS	2007	DBLP DOI BibTeX RDF
1	T.-L. Hung, J.-L. Huang	A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing.	VTS	2007	DBLP DOI BibTeX RDF
1	Jaehoon Song, Piljae Min, Hyunbean Yi, Sungju Park	Design of Test Access Mechanism for AMBA-Based System-on-a-Chip.	VTS	2007	DBLP DOI BibTeX RDF
1	Simon P. Wilson 0001, Ben Flood, Suresh Goyal, Jim Mosher, Susan Bergin, Joseph O'Brien, Robert Kennedy	Parameter Estimation for a Model with Both Imperfect Test and Repair.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes 0001	DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.	VTS	2007	DBLP DOI BibTeX RDF
1	Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li 0001, Alex Pao, Kevin Chiu, Eliot Chen	A Built-In Self-Repair Scheme for Multiport RAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Optimizing Test Length for Soft Faults in DRAM Devices.	VTS	2007	DBLP DOI BibTeX RDF	DRAM testing, test length optimization, circuit design, memory layout, delay time, soft faults
1	Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang	Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.	VTS	2007	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Full Open Defects in Interconnecting Lines.	VTS	2007	DBLP DOI BibTeX RDF	Defect Diagnosis, Full Open Defect, Interconnecting Line, CMOS
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.	VTS	2007	DBLP DOI BibTeX RDF	Current Based Diagnosis, Current Signatures, I_DDQ, Very Low Voltage, CMOS, Bridging Defect
1	Byoungho Kim, Zhenhai Fu, Jacob A. Abraham	Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications.	VTS	2007	DBLP DOI BibTeX RDF
1	K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula	Power Virus Generation Using Behavioral Models of Circuits.	VTS	2007	DBLP DOI BibTeX RDF	Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
1	Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu	SDRAM Delay Fault Modeling and Performance Testing.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	Peter Wohl, John A. Waicukauski, Sanjay Patel	Automated Design and Insertion of Optimal One-Hot Bus Encoders.	VTS	2007	DBLP DOI BibTeX RDF
1	Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini	Minimizing the Impact of Scan Compression.	VTS	2007	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Jing Huang 0001, Fabrizio Lombardi	Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets.	VTS	2007	DBLP DOI BibTeX RDF	snake tile set, nanotechnology, error resilience, error tolerance, DNA Self-assembly
1	Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware	Silicon Evaluation of Static Alternative Fault Models.	VTS	2007	DBLP DOI BibTeX RDF
1	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara	Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.	VTS	2007	DBLP DOI BibTeX RDF	multi-clock domain, wrapper design, SoC, test scheduling, embedded core test
1	Hsiang-Hui Huang, Ching-Hwa Cheng	Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit.	VTS	2007	DBLP DOI BibTeX RDF
1	Chunsheng Liu, Yu Huang 0005	Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance.	VTS	2007	DBLP DOI BibTeX RDF
1	Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
1	Brian Mullins, Hossein Asadi 0001, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano	Case Study: Soft Error Rate Analysis in Storage Systems.	VTS	2007	DBLP DOI BibTeX RDF
1	John P. Hayes, Ilia Polian, Bernd Becker 0001	An Analysis Framework for Transient-Error Tolerance.	VTS	2007	DBLP DOI BibTeX RDF
1	Vishwanath Natarajan, Ganesh Srinivasan, Abhijit Chatterjee, Craig Force	Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios.	VTS	2007	DBLP DOI BibTeX RDF
1	Le Jin, Degang Chen 0001, Randall L. Geiger	Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal.	VTS	2007	DBLP DOI BibTeX RDF
1	Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Low Power Embedded Deterministic Test.	VTS	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.	VTS	2007	DBLP DOI BibTeX RDF
1	Jinkyu Lee 0005, Nur A. Touba	Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding.	VTS	2006	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram	Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.	VTS	2006	DBLP DOI BibTeX RDF
1	Wojciech Rajski, Janusz Rajski	Modular Compactor of Test Responses.	VTS	2006	DBLP DOI BibTeX RDF
1	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Davide Appello	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF	Probing technologies and probe cards, reduced pin count testing, multi-site efficiency, reconfigurable test resources and test resource partitioning, test generation and diagnosis, built-in and built-off DFT, test economics
1		Test Technology Technical Council (TTTC).	VTS	2006	DBLP DOI BibTeX RDF
1		Organizing Committee.	VTS	2006	DBLP DOI BibTeX RDF
1	Bharath Seshadri, Xiaoming Yu, Srikanth Venkataraman	Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification.	VTS	2006	DBLP DOI BibTeX RDF
1	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Scan Tests with Multiple Fault Activation Cycles for Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
1	Avijit Dutta, Nur A. Touba	Iterative OPDD Based Signal Probability Calculation.	VTS	2006	DBLP DOI BibTeX RDF
1	Yervant Zorian, Bruce C. Kim	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.	VTS	2006	DBLP DOI BibTeX RDF
1	Vishnu C. Vimjam, Michael S. Hsiao	Efficient Fault Collapsing via Generalized Dominance Relations.	VTS	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy	Dominance Based Analysis for Large Volume Production Fail Diagnosis.	VTS	2006	DBLP DOI BibTeX RDF
1	Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara	BIST Pretest of ICs: Risks and Benefits.	VTS	2006	DBLP DOI BibTeX RDF
1		Forward.	VTS	2006	DBLP DOI BibTeX RDF
1	Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami	Improved Handling of False and Multicycle Paths in ATPG.	VTS	2006	DBLP DOI BibTeX RDF
1	Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic	A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.	VTS	2006	DBLP DOI BibTeX RDF
1	Quming Zhou, Mihir R. Choudhury, Kartik Mohanram	Design Optimization for Robustness to Single Event Upsets.	VTS	2006	DBLP DOI BibTeX RDF
1	Jason G. Brown, R. D. (Shawn) Blanton	Exploiting Regularity for Inductive Fault Analysis.	VTS	2006	DBLP DOI BibTeX RDF
1	Cheng-Wen Wu	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Sai Raghuram Durbha, Amit Laknaur, Haibo Wang 0005	Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques.	VTS	2006	DBLP DOI BibTeX RDF
1	Bernard Courtois	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1		Acknowledgments.	VTS	2006	DBLP DOI BibTeX RDF
1	Kazumi Hatayama	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Richard Putman, Rahul Gawde	Enhanced Timing-Based Transition Delay Testing for Small Delay Defects.	VTS	2006	DBLP DOI BibTeX RDF
1	Hsieh-Hung Hsieh, Liang-Hung Lu	Integrated CMOS Power Sensors for RF BIST Applications.	VTS	2006	DBLP DOI BibTeX RDF
1	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries.	VTS	2006	DBLP DOI BibTeX RDF
1		Test Technology Educational Program (TTEP) Tutorials.	VTS	2006	DBLP DOI BibTeX RDF
1	Hongjoong Shin, Byoungho Kim, Jacob A. Abraham	Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.	VTS	2006	DBLP DOI BibTeX RDF
1		Steering Committee.	VTS	2006	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
1	Kee Sup Kim, Mohammad Tehranipoor	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Rajesh Galivanche, Bob Gottlieb	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Minsik Cho, David Z. Pan	PEAKASO: Peak-Temperature Aware Scan-Vector Optimization.	VTS	2006	DBLP DOI BibTeX RDF
1	Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	On the Automation of the Test Flow of Complex SoCs.	VTS	2006	DBLP DOI BibTeX RDF
1	Michael Nicolaidis	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.	VTS	2006	DBLP DOI BibTeX RDF
1	Vishwanath Natarajan, Soumendu Bhattacharya, Abhijit Chatterjee	Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors.	VTS	2006	DBLP DOI BibTeX RDF

Publications at "VTS"( http://dblp.L3S.de/Venues/VTS )