Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Moinuddin K. Qureshi	CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping.	MICRO	2018	DBLP DOI BibTeX RDF
17	Rui Zhang 0068, Calvin Deutschbein, Peng Huang 0005, Cynthia Sturton	End-to-End Automated Exploit Generation for Validating the Security of Processor Designs.	MICRO	2018	DBLP DOI BibTeX RDF
17	Caroline Trippel, Daniel Lustig, Margaret Martonosi	CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests.	MICRO	2018	DBLP DOI BibTeX RDF
17	Michael B. Sullivan 0001, Siva Kumar Sastry Hari, Brian Zimmer, Timothy Tsai 0002, Stephen W. Keckler	SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection.	MICRO	2018	DBLP DOI BibTeX RDF
17	Tao Chen 0045, Shreesha Srinath, Christopher Batten, G. Edward Suh	An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware.	MICRO	2018	DBLP DOI BibTeX RDF
17	Ananda Samajdar, Parth Mannan, Kartikay Garg, Tushar Krishna	GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware.	MICRO	2018	DBLP DOI BibTeX RDF
17	Srikant Bharadwaj, Guilherme Cox, Tushar Krishna, Abhishek Bhattacharjee	Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects.	MICRO	2018	DBLP DOI BibTeX RDF
17	Yirong Lv, Bin Sun, Qingyi Luo, Jing Wang 0055, Zhibin Yu 0001, Xuehai Qian	CounterMiner: Mining Big Performance Data from Hardware Counters.	MICRO	2018	DBLP DOI BibTeX RDF
17	Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt	Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication.	MICRO	2018	DBLP DOI BibTeX RDF
17	Yaohua Wang, Arash Tavakkol, Lois Orosa 0001, Saugata Ghose, Nika Mansouri-Ghiasi, Minesh Patel, Jeremie S. Kim, Hasan Hassan, Mohammad Sadrosadati, Onur Mutlu	Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.	MICRO	2018	DBLP DOI BibTeX RDF
17	Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi J. Kurdahi, Ahmed M. Eltawil, Nikil D. Dutt	Microarchitecture-Level SoC Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
17	Jack Doweck, Wen-Fu Kao, Allen Kuan-yu Lu, Julius Mandelblat, Anirudha Rahatekar, Lihu Rappoport, Efraim Rotem, Ahmad Yasin, Adi Yoaz	Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake.	IEEE Micro	2017	DBLP DOI BibTeX RDF
17	Zohre Mohammadi-Arfa, Ali Jahanian 0001	DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design.	IEEE Trans. Biomed. Circuits Syst.	2017	DBLP DOI BibTeX RDF
17	Xiang Fu 0003, M. A. Rol, Cornelis Christiaan Bultink, J. van Someren 0001, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels	An Experimental Microarchitecture for a Superconducting Quantum Processor.	CoRR	2017	DBLP BibTeX RDF
17	Xiangyu Guo, Qi Chu 0003, Shin Kee Chung, Zhihui Du, LinQing Wen	Acceleration of low-latency gravitational wave searches using Maxwell-microarchitecture GPUs.	CoRR	2017	DBLP BibTeX RDF
17	Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri	The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes.	CoRR	2017	DBLP BibTeX RDF
17	Yangdong Deng, Yufei Ni, Zonghui Li, Shuai Mu 0002, Wenjun Zhang	Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques.	ACM Comput. Surv.	2017	DBLP DOI BibTeX RDF
17	Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Maurizio Iacaruso, Mauro Pipponzi, Riccardo Mariani, Stefano Di Carlo	RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.	DSN Workshops	2017	DBLP DOI BibTeX RDF
17	Botao Deng, Anas Z. Abidin, Adora M. D'Souza, Mahesh B. Nagarajan, Paola Coan, Axel Wismüller	Characterizing cartilage microarchitecture on phase-contrast x-ray computed tomography using deep learning with convolutional neural networks.	Medical Imaging: Computer-Aided Diagnosis	2017	DBLP DOI BibTeX RDF
17	Hillery C. Hunter, Jaime Moreno 0002, Joel S. Emer, Daniel Sánchez 0003 (eds.)	Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017	MICRO	2017	DBLP DOI BibTeX RDF
17	Alexander Antonov, Pavel Kustarev, Sergey Bikovsky	Improving microarchitecture design and hardware generation using micro-language IP cores.	NORCAS	2017	DBLP DOI BibTeX RDF
17	Alessandro Vallero, Stefano Di Carlo, Sotiris Tselonis, Dimitris Gizopoulos	Microarchitecture level reliability comparison of modern GPU designs: First findings.	ISPASS	2017	DBLP DOI BibTeX RDF
17	Yi Dai, Kefei Wang, Gang Qu 0001, Liquan Xiao, Dezun Dong, Xingyun Qi	A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design.	IPDPS	2017	DBLP DOI BibTeX RDF
17	Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri	The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.	ApplePies	2017	DBLP DOI BibTeX RDF
17	Xiuxia Zhang, Guangming Tan, Shuangbai Xue, Jiajia Li 0001, Keren Zhou 0001, Mingyu Chen 0001	Understanding the GPU Microarchitecture to Achieve Bare-Metal Performance Tuning.	PPoPP	2017	DBLP DOI BibTeX RDF
17	Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio González 0001	MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.	ISCA	2017	DBLP DOI BibTeX RDF
17	Andrea Mondelli	Revisiting Wide Superscalar Microarchitecture.		2017	RDF
17	Ya-Shuai Lü, Libo Huang, Li Shen 0007, Zhiying Wang 0003	Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling.	MICRO	2017	DBLP DOI BibTeX RDF
17	Mostafa Mahmoud, Bojian Zheng, Alberto Delmas Lascorz, Felix Heide, Jonathan Assouline, Paul Boucher, Emmanuel Onzon, Andreas Moshovos	IDEAL: image denoising accelerator.	MICRO	2017	DBLP DOI BibTeX RDF
17	Swamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi	Taming the instruction bandwidth of quantum computers via hardware-managed error correction.	MICRO	2017	DBLP DOI BibTeX RDF
17	Md. Enamul Haque, Yuxiong He, Sameh Elnikety, Thu D. Nguyen, Ricardo Bianchini, Kathryn S. McKinley	Exploiting heterogeneity for tail latency and energy efficiency.	MICRO	2017	DBLP DOI BibTeX RDF
17	Zhaoxia Deng, Lunkai Zhang, Nikita Mishra, Henry Hoffmann, Frederic T. Chong	Memory cocktail therapy: a general learning-based framework to optimize dynamic tradeoffs in NVMs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson 0002, Aditya Agrawal, Stephen W. Keckler, William J. Dally	Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.	MICRO	2017	DBLP DOI BibTeX RDF
17	George Papadimitriou 0001, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das	Harnessing voltage margins for energy efficiency in multicore CPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Sandeep R. Agrawal, Sam Idicula, Arun Raghavan, Evangelos Vlachos, Venkatraman Govindaraju, Venkatanathan Varadarajan, Cagri Balkesen, Georgios Giannikis, Charlie Roth, Nipun Agarwal, Eric Sedlar	A many-core architecture for in-memory data processing.	MICRO	2017	DBLP DOI BibTeX RDF
17	Xulong Tang, Orhan Kislal, Mahmut T. Kandemir, Mustafa Karaköy	Data movement aware computation partitioning.	MICRO	2017	DBLP DOI BibTeX RDF
17	Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie S. Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry	Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology.	MICRO	2017	DBLP DOI BibTeX RDF
17	Daphne I. Gorman, Matthew R. Guthaus, Jose Renau	Architectural opportunities for novel dynamic EMI shifting (DEMIS).	MICRO	2017	DBLP DOI BibTeX RDF
17	Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramírez, David W. Nellans	Beyond the socket: NUMA-aware GPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Jongse Park, Hardik Sharma, Divya Mahajan 0001, Joon Kyung Kim, Preston Olds, Hadi Esmaeilzadeh	Scale-out acceleration for machine learning.	MICRO	2017	DBLP DOI BibTeX RDF
17	Hoda Naghibijouybari, Khaled N. Khasawneh, Nael B. Abu-Ghazaleh	Constructing and characterizing covert channels on GPGPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Youngsok Kim, Jae-Eon Jo, Hanhwi Jang, Minsoo Rhu, Hanjun Kim 0001, Jangwoo Kim	GPUpd: a fast and scalable multi-GPU architecture using cooperative projection and distribution.	MICRO	2017	DBLP DOI BibTeX RDF
17	Pedro Duarte, Pedro Tomás, Gabriel Falcão 0001	SCRATCH: an end-to-end application-aware soft-GPGPU architecture and trimming tool.	MICRO	2017	DBLP DOI BibTeX RDF
17	Kaisheng Ma, Xueqing Li, Jinyang Li 0002, Yongpan Liu, Yuan Xie 0001, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan	Incidental computing on IoT nonvolatile processors.	MICRO	2017	DBLP DOI BibTeX RDF
17	Caiwen Ding, Siyu Liao, Yanzhi Wang, Zhe Li 0001, Ning Liu 0007, Youwei Zhuo, Chao Wang 0051, Xuehai Qian, Yu Bai 0004, Geng Yuan, Xiaolong Ma, Yipeng Zhang, Jian Tang 0008, Qinru Qiu, Xue Lin, Bo Yuan 0001	CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices.	MICRO	2017	DBLP DOI BibTeX RDF
17	Jorge Albericio, Alberto Delmas, Patrick Judd, Sayeh Sharify, Gerard O'Leary, Roman Genov, Andreas Moshovos	Bit-pragmatic deep neural network computing.	MICRO	2017	DBLP DOI BibTeX RDF
17	Daniel A. Jiménez, Elvira Teran	Multiperspective reuse prediction.	MICRO	2017	DBLP DOI BibTeX RDF
17	Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie 0001	DRISA: a DRAM-based reconfigurable in-situ accelerator.	MICRO	2017	DBLP DOI BibTeX RDF
17	Khaled N. Khasawneh, Nael B. Abu-Ghazaleh, Dmitry Ponomarev 0001, Lei Yu 0001	RHMD: evasion-resilient hardware malware detectors.	MICRO	2017	DBLP DOI BibTeX RDF
17	Yuanfeng Peng, Benjamin P. Wood, Joseph Devietti	PARSNIP: performant architecture for race safety with no impact on precision.	MICRO	2017	DBLP DOI BibTeX RDF
17	Parker Hill, Animesh Jain, Mason Hill, Babak Zamirai, Chang-Hong Hsu, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars	DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fission.	MICRO	2017	DBLP DOI BibTeX RDF
17	Prathmesh Kallurkar, Smruti R. Sarangi	Schedtask: a hardware-assisted task scheduler.	MICRO	2017	DBLP DOI BibTeX RDF
17	Yuanwei Fang, Chen Zou 0001, Aaron J. Elmore, Andrew A. Chien	UDP: a programmable accelerator for extract-transform-load workloads and more.	MICRO	2017	DBLP DOI BibTeX RDF
17	John Kloosterman, Jonathan Beaumont, Davoud Anoushe Jamshidi, Jonathan Bailey, Trevor N. Mudge, Scott A. Mahlke	Regless: just-in-time operand staging for GPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Weilong Cui, Timothy Sherwood	Estimating and understanding architectural risk.	MICRO	2017	DBLP DOI BibTeX RDF
17	AmirAli Abdolrashidi, Devashree Tripathy, Mehmet Esat Belviranli, Laxmi Narayan Bhuyan, Daniel Wong 0001	Wireframe: supporting data-dependent parallelism through dependency graph execution in GPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Seunghee Shin, Satish Kumar Tirukkovalluri, James Tuck 0001, Yan Solihin	Proteus: a flexible and fast software supported hardware logging approach for NVM.	MICRO	2017	DBLP DOI BibTeX RDF
17	Christian DeLozier, Ariel Eizenberg, Shiliang Hu, Gilles Pokam, Joseph Devietti	TMI: thread memory isolation for false sharing repair.	MICRO	2017	DBLP DOI BibTeX RDF
17	Gunjae Koo, Kiran Kumar Matam, Te I, H. V. Krishna Giri Narra, Jing Li 0021, Hung-Wei Tseng 0001, Steven Swanson, Murali Annavaram	Summarizer: trading communication with computing near storage.	MICRO	2017	DBLP DOI BibTeX RDF
17	Samira Manabi Khan, Chris Wilkerson, Zhe Wang 0023, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu	Detecting and mitigating data-dependent DRAM failures by exploiting current memory content.	MICRO	2017	DBLP DOI BibTeX RDF
17	Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke	Mirage cores: the illusion of many out-of-order cores using in-order hardware.	MICRO	2017	DBLP DOI BibTeX RDF
17	Dimitrios Skarlatos 0002, Nam Sung Kim, Josep Torrellas	Pageforge: a near-memory content-aware page-merging architecture.	MICRO	2017	DBLP DOI BibTeX RDF
17	Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten	Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Joonmoo Huh, James Tuck 0001	Improving the effectiveness of searching for isomorphic chains in superword level parallelism.	MICRO	2017	DBLP DOI BibTeX RDF
17	Haibo Zhang 0005, Prasanna Venkatesh Rengasamy, Shulin Zhao 0001, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut T. Kandemir, Ravi R. Iyer 0001, Chita R. Das	Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handhelds.	MICRO	2017	DBLP DOI BibTeX RDF
17	Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas	Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation.	MICRO	2017	DBLP DOI BibTeX RDF
17	Ali JavadiAbhari, Pranav Gokhale, Adam Holmes, Diana Franklin, Kenneth R. Brown, Margaret Martonosi, Frederic T. Chong	Optimized surface code communication in superconducting quantum computers.	MICRO	2017	DBLP DOI BibTeX RDF
17	Rachata Ausavarungnirun, Joshua Landgraf, Vance Miller, Saugata Ghose, Jayneel Gandhi, Christopher J. Rossbach, Onur Mutlu	Mosaic: a GPU memory manager with application-transparent support for multiple page sizes.	MICRO	2017	DBLP DOI BibTeX RDF
17	Ang Li 0006, Wenfeng Zhao, Shuaiwen Leon Song	BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors.	MICRO	2017	DBLP DOI BibTeX RDF
17	Ivan Tanasic, Isaac Gelado, Marc Jordà, Eduard Ayguadé, Nacho Navarro	Efficient exception handling support for GPUs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Reza Yazdani, José-María Arnau, Antonio González 0001	UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition.	MICRO	2017	DBLP DOI BibTeX RDF
17	Guoyang Chen, Lei Zhang, Richa Budhiraja, Xipeng Shen, Youfeng Wu	Efficient support of position independence on non-volatile memory.	MICRO	2017	DBLP DOI BibTeX RDF
17	Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar 0002, John Sartori	Software-based gate-level information flow security for IoT systems.	MICRO	2017	DBLP DOI BibTeX RDF
17	Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer	RTLcheck: verifying the memory consistency of RTL designs.	MICRO	2017	DBLP DOI BibTeX RDF
17	Zecheng He, Ruby B. Lee	How secure is your cache against side-channel attacks?	MICRO	2017	DBLP DOI BibTeX RDF
17	Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song 0007, Lizy K. John	CSALT: context switch aware large TLB.	MICRO	2017	DBLP DOI BibTeX RDF
17	Tiancong Wang, Sakthikumaran Sambasivam, Yan Solihin, James Tuck 0001	Hardware supported persistent object address translation.	MICRO	2017	DBLP DOI BibTeX RDF
17	Yipeng Huang 0001, Ning Guo, Mingoo Seok, Yannis P. Tsividis, Kyle T. Mandli, Simha Sethumadhavan	Hybrid analog-digital solution of nonlinear partial differential equations.	MICRO	2017	DBLP DOI BibTeX RDF
17	Thomas J. Repetti, João Pedro Cerqueira, Martha A. Kim, Mingoo Seok	Pipelining a triggered processing element.	MICRO	2017	DBLP DOI BibTeX RDF
17	Rami Sheikh, Harold W. Cain, Raguram Damodaran	Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores.	MICRO	2017	DBLP DOI BibTeX RDF
17	Aditya Agrawal, Josep Torrellas, Sachin Idgunji	Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks.	MICRO	2017	DBLP DOI BibTeX RDF
17	Zhen Zheng, Chanyoung Oh, Jidong Zhai, Xipeng Shen, Youngmin Yi, Wenguang Chen	Versapipe: a versatile programming framework for pipelined computing on GPU.	MICRO	2017	DBLP DOI BibTeX RDF
17	Ting-Jung Chang, Zhuozhi Yao, Paul J. Jackson, Barry P. Rand, David Wentzlaff	Architectural tradeoffs for biodegradable computing.	MICRO	2017	DBLP DOI BibTeX RDF
17	Abhishek Bhattacharjee	Using branch predictors to predict brain activity in brain-machine implants.	MICRO	2017	DBLP DOI BibTeX RDF
17	Opeoluwa Matthews, Daniel J. Sorin	Architecting hierarchical coherence protocols for push-button parametric verification.	MICRO	2017	DBLP DOI BibTeX RDF
17	Arun Subramaniyan 0001, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das	Cache automaton.	MICRO	2017	DBLP DOI BibTeX RDF
17	Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad	Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.	MICRO	2017	DBLP DOI BibTeX RDF
17	Henry Wong, Vaughn Betz, Jonathan Rose	Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System.	ACM Trans. Reconfigurable Technol. Syst.	2016	DBLP DOI BibTeX RDF
17	Yumin Hou, Hu He 0001, Xu Yang 0003, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu	FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.	VLSI Design	2016	DBLP DOI BibTeX RDF
17	Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. Holbert	An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
17	Jason Cong, Peng Li 0031, Bingjun Xiao, Peng Zhang 0007	An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
17	Myoungsoo Jung, Wonil Choi, Shuwen Gao, Ellis Herbert Wilson III, David Donofrio, John Shalf, Mahmut Taylan Kandemir	NANDFlashSim: High-Fidelity, Microarchitecture-Aware NAND Flash Memory Simulation.	ACM Trans. Storage	2016	DBLP DOI BibTeX RDF
17	Ittai Anati, David Blythe, Jack Doweck, Hong Jiang, Wen-Fu Kao, Julius Mandelblat, Lihu Rappoport, Efraim Rotem, Ahmad Yasin	Inside 6th gen Intel® Core™: New microarchitecture code named skylake.	Hot Chips Symposium	2016	DBLP DOI BibTeX RDF
17		49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016	MICRO	2016	DBLP BibTeX RDF
17	Sina Hassani, Gabriel Southern, Jose Renau	LiveSim: Going live with microarchitecture simulation.	HPCA	2016	DBLP DOI BibTeX RDF
17	Johannes Hofmann 0001, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein	Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks.	ARCS	2016	DBLP DOI BibTeX RDF
17	Athanasios Chatzidimitriou, Dimitris Gizopoulos	Anatomy of microarchitecture-level reliability assessment: Throughput and accuracy.	ISPASS	2016	DBLP DOI BibTeX RDF
17	Shao-Chung Wang, Li-Chen Kan, Yuan-Shin Hwang, Jenq Kuen Lee	Energy Efficient Affine Register File for GPU Microarchitecture.	ICPP Workshops	2016	DBLP DOI BibTeX RDF
17	Sotiris Tselonis, Manolis Kaliorakis, Nikos Foutris, George Papadimitriou 0001, Dimitris Gizopoulos	Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level.	VTS	2016	DBLP DOI BibTeX RDF
17	Cunlu Li, Dezun Dong, Xiangke Liao, Ji Wu 0006, Fei Lei	RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer.	Hot Interconnects	2016	DBLP DOI BibTeX RDF