Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Stephan Diestelhorst	Interaction of hardware transactional memory and microprocessor microarchitecture.		2019	RDF
12	Gaurav Rajavendra Reddy, Yiorgos Makris	Design Space Exploration for Hotspot Detection.	MTV	2019	DBLP DOI BibTeX RDF
12	Sherif Hosny, Amr Baher	Design Crawler: A Web Application for Digital Design Metadata Analysis.	MTV	2019	DBLP DOI BibTeX RDF
12	Annachiara Ruospo, Ernesto Sánchez 0001	On the Detection of Always-On Hardware Trojans Supported by a Pre-Silicon Verification Methodology.	MTV	2019	DBLP DOI BibTeX RDF
12	Mikhail M. Chupilko, Alexander Kamkin, Alexander Protsenko	Open-Source Validation Suite for RISC-V.	MTV	2019	DBLP DOI BibTeX RDF
12	Jeff Scott, Jonathan Sadowsky, Jigar Savla	RamGen: Moving Memories from Physical to the Logical Domain.	MTV	2019	DBLP DOI BibTeX RDF
12	Prokash Ghosh, Rohit Srivastava	Case Study: SoC Performance Verification and Static Verification of RTL Parameters.	MTV	2019	DBLP DOI BibTeX RDF
12	Jinsae Jung, Jaeun Park, Apurva Kumar	A Verification Framework of Neural Processing Unit for Super Resolution.	MTV	2019	DBLP DOI BibTeX RDF
12	Mir Tanjidur Rahman, Navid Asadizanjani	Backside Security Assessment of Modern SoCs.	MTV	2019	DBLP DOI BibTeX RDF
12	Ahmed Wahba, Justin Hohnerlein, Farhan Rahman	Expediting Design Bug Discovery in Regressions of x86 Processors Using Machine Learning.	MTV	2019	DBLP DOI BibTeX RDF
12	Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra	Techniques for Debug of Low Power SoCs.	MTV	2019	DBLP DOI BibTeX RDF
12	Jigar Savla	Smarter Disk Space Management for Silicon Workflows.	MTV	2019	DBLP DOI BibTeX RDF
12	Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo	Hardware and Software Co-Verification from Security Perspective.	MTV	2019	DBLP DOI BibTeX RDF
12	Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib	Multilayer Camouflaged Secure Boot for SoCs.	MTV	2019	DBLP DOI BibTeX RDF
12	Hongyang Jia, Naveen Verma	Exploiting Approximate Feature Extraction via Genetic Programming for Hardware Acceleration in a Heterogeneous Microprocessor.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Jiangyi Li, Teng Yang, Minhao Yang, Peter R. Kinget, Mingoo Seok	An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Tze Sin Tan, Bakhtiar Affendi Rosdi	Hardware-assisted Verilog simulation system using an application specific microprocessor.	Integr.	2018	DBLP DOI BibTeX RDF
12	Anteneh Gebregiorgis, Mehdi Baradaran Tahoori	Fine-Grained Energy-Constrained Microprocessor Pipeline Design.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
12	Martin Schoeberl, Wolfgang Puffitsch, Stefan Hepp, Benedikt Huber, Daniel Prokesch	Patmos: a time-predictable microprocessor.	Real Time Syst.	2018	DBLP DOI BibTeX RDF
12	Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jaime Jimenez, Jesús Lázaro 0001	SEU emulation in industrial SoCs combining microprocessor and FPGA.	Reliab. Eng. Syst. Saf.	2018	DBLP DOI BibTeX RDF
12	Christian Jacobi 0002, Anthony Saporito, Martin Recktenwald, Aaron Tsai, Ulrich Mayer, Markus M. Helms, Adam Collura, Pak-kin Mak, Robert J. Sonnelitter, Michael A. Blake, Tim Bronson, Arthur O'neill, Vesselina K. Papazova	Design of the IBM z14 microprocessor.	IBM J. Res. Dev.	2018	DBLP DOI BibTeX RDF
12	Ebrahim Abiri, Abdolreza Darabi	A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
12	Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross	Microprocessor Optimizations for the Internet of Things: A Survey.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
12	Hongyang Jia, Yinqi Tang, Hossein Valavi, Jintao Zhang, Naveen Verma	A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing.	CoRR	2018	DBLP BibTeX RDF
12	Vytautas Markevicius, Dangirutis Navikas, Adam Idzkowski, Darius Andriukaitis, Algimantas Valinevicius, Mindaugas Zilys	Practical Methods for Vehicle Speed Estimation Using a Microprocessor-Embedded System with AMR Sensors.	Sensors	2018	DBLP DOI BibTeX RDF
12	Yu Sang Chang, Jinsoo Lee, Yun Seok Jung	Are technology improvement rates of knowledge industries following Moore's law? An empirical study of microprocessor, mobile cellular, and genome sequencing technologies.	Int. J. Technol. Manag.	2018	DBLP DOI BibTeX RDF
12		19th International Workshop on Microprocessor and SOC Test and Verification, MTV 2018, Austin, TX, USA, December 9-10, 2018	MTV	2018	DBLP BibTeX RDF
12	Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris	Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs.	PATMOS	2018	DBLP DOI BibTeX RDF
12	S. G. Solovyov, E. R. Milutin, V. A. Ryzhikov	Improvement of the Design of a Microprocessor-Based Power Supply Control System of an Internal Combustion Engine.	EWDTS	2018	DBLP DOI BibTeX RDF
12	Md. Tobibul Islam, Mohiuddin Ahmad, Akash Shingha Bappy	Microprocessor-Based Smart Blind Glass System for Visually Impaired People.	IJCCI	2018	DBLP DOI BibTeX RDF
12	Roel Uytterhoeven, Wim Dehaene	A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI.	ESSCIRC	2018	DBLP DOI BibTeX RDF
12	Tianyu Jia, Russ Joseph, Jie Gu 0001	An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor.	ESSCIRC	2018	DBLP DOI BibTeX RDF
12	Grzegorz Komor, Michal Nowicki 0002, Klaudia Bis, Roman Szewczyk	Microprocessor Based Assmann Psychrometer.	AUTOMATION	2018	DBLP DOI BibTeX RDF
12	Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell 0001, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert 0001, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi 0002, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves 0002	IBM z14™: 14nm microprocessor for the next-generation mainframe.	ISSCC	2018	DBLP DOI BibTeX RDF
12	Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez 0001, Matteo Sonza Reorda	About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.	LATS	2018	DBLP DOI BibTeX RDF
12	Andrea Marcelli, Ernesto Sánchez 0001, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti 0003, Davide Pola, Alessandro Salvato, Michele Simili	Defeating hardware Trojan in microprocessor cores through software obfuscation.	LATS	2018	DBLP DOI BibTeX RDF
12	Jingyong Cai, Masashi Takemoto, Hironori Nakajo	Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices.	GCCE	2018	DBLP DOI BibTeX RDF
12	Krzysztof Krupa, Marcin Grochowina	Microprocessor implementation of the sound source location process based on the correlation of signals.	SPA	2018	DBLP DOI BibTeX RDF
12	Manolis Kaliorakis	Methodologies for accelerated analysis of the reliability and the energy efficiency levels of modern microprocessor architectures		2018	RDF
12	Glenn Coates	A syntax directed imperative language microprocessor for reduced power consumption and improved performance.		2018	RDF
12	Yanhua Cao, Osama Shoubber, Pallavi Jesrani	Automatic Debug Quantification for Workload Balance and Progress Tracking.	MTV	2018	DBLP DOI BibTeX RDF
12	Asif Jafri, Jung-Wook Kim	Proving the Capability of Arm IP for Functional Safety Applications.	MTV	2018	DBLP DOI BibTeX RDF
12	Mikhail M. Chupilko, Alexander Kamkin, Artem Kotsynyak, Alexander Protsenko, Sergey A. Smolov, Andrei Tatarnikov	Test Program Generator MicroTESK for RISC-V.	MTV	2018	DBLP DOI BibTeX RDF
12	Chetas Mapara, Priti Nagarajan	Transaction Based Speedup for Simulation Replay.	MTV	2018	DBLP DOI BibTeX RDF
12	Rekha Bangalore, Adeosun luwatosin Oluwatosin, Kelvin K. Lam	Schmoo Data Analysis Using Machine Language Algorithms.	MTV	2018	DBLP DOI BibTeX RDF
12	Jigar Savla	Getting Started on Co-Emulation: Transition your Design and Testbench to an Emulator.	MTV	2018	DBLP DOI BibTeX RDF
12	Siroos Madani, Mohammad R. Madani, Magdy A. Bayoumi	A Perceptron-Inspired Technique for Hardware Obfuscation.	MTV	2018	DBLP DOI BibTeX RDF
12	Abdelfattah Munir, Mina Magdy, Samer Ahmed, Sherouk Nasr, Sameh El-Ashry, Ahmed Shalaby 0001	Fast Reliable Verification Methodology for RISC-V Without a Reference Model.	MTV	2018	DBLP DOI BibTeX RDF
12	Manish Kumar Agarwal, Amandeep Sharan, Mohammad Asif Khan 0002, Atul Gupta	Multi-Master Validation Framework for Next Generation Automotive SOCs.	MTV	2018	DBLP DOI BibTeX RDF
12	Rekha Bangalore, Raji M. Bandanapudi	Application of Combinatorial Test (CT) Algorithm for Protocol and Hardware Feature Validation.	MTV	2018	DBLP DOI BibTeX RDF
12	Ayushi Agarwal, Pankaj Gupta, Atul Gupta	Advanced Regression Management for Post-Silicon Validation of Automotive SOCs.	MTV	2018	DBLP DOI BibTeX RDF
12	Shelly Henry, Nirabh Regmi	How to Close Coverage 10x Faster using Portable Stimulus Standard - A Case Study.	MTV	2018	DBLP DOI BibTeX RDF
12	Pratheema Mohandoss, Archana Rengaraj	Pre-Silicon DFT Verification on SOC Slim Model.	MTV	2018	DBLP DOI BibTeX RDF
12	Calvin Deutschbein, Cynthia Sturton	Mining Security Critical Linear Temporal Logic Specifications for Processors.	MTV	2018	DBLP DOI BibTeX RDF
12	Sameh El-Ashry, Ahmed Adel	Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage.	MTV	2018	DBLP DOI BibTeX RDF
12	Harry Foster	2018 FPGA Functional Verification Trends.	MTV	2018	DBLP DOI BibTeX RDF
12	Amr Moursi, Romaisaa Samhoud, Yaseen Kamal, Mazen Magdy, Sameh El-Ashry, Ahmed Shalaby 0001	Different Reference Models for UVM Environment to Speed Up the Verification Time.	MTV	2018	DBLP DOI BibTeX RDF
12	Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy	Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
12	Taeyoung Kim 0001, Zeyu Sun 0001, Hai-Bao Chen, Hai Wang 0002, Sheldon X.-D. Tan	Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor Considering Both Hard and Soft Errors.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
12	Nastaran Rajaei, Ramin Rajaei, Mahmoud Tabandeh	A soft error tolerant register file for highly reliable microprocessor design.	Int. J. High Perform. Syst. Archit.	2017	DBLP DOI BibTeX RDF
12	Muiris Woulfe, Michael Manzke	A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection.	EURASIP J. Embed. Syst.	2017	DBLP DOI BibTeX RDF
12	Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, Seyed Vahid Azhari	Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.	IET Comput. Digit. Tech.	2017	DBLP DOI BibTeX RDF
12	Stephen P. Morse	The Intel 8086 Chip and the Future of Microprocessor Design.	Computer	2017	DBLP DOI BibTeX RDF
12	Shunji Nakata, Masaki Ono, Masato Sakitani	An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
12	Aymen Touati, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda	Microprocessor Testing: Functional Meets Structural Test.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
12	Eric Jonas, Konrad Paul Körding	Could a Neuroscientist Understand a Microprocessor?	PLoS Comput. Biol.	2017	DBLP DOI BibTeX RDF
12	Sai Manoj P. D., Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu 0002, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu 0001	A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
12		18th International Workshop on Microprocessor and SOC Test and Verification, MTV 2017, Austin, TX, USA, December 11-12, 2017	MTV	2017	DBLP BibTeX RDF
12	Dipanjan Bhadra, Kenneth S. Stevens	Design of a low power, relative timing based asynchronous MSP430 microprocessor.	DATE	2017	DBLP DOI BibTeX RDF
12	Masaru Kudo, Kimiyoshi Usami	Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor.	NVMSA	2017	DBLP DOI BibTeX RDF
12	Young H. Cho, Siddharth S. Bhargav	Fine-grained on-line power monitoring for soft microprocessor based system-on-chip.	ReConFig	2017	DBLP DOI BibTeX RDF
12	Yoichi Masuda, Yuki Minami, Masato Ishikawa	Actuator synchronization for adaptive motion generation without any sensor or microprocessor.	ASCC	2017	DBLP DOI BibTeX RDF
12	Hirano Saburo, Ochi Akiko	Case Study of a Sensor Platform System Using the Wireless Microprocessor Module TWE-LITE for Media Art and Computer Music.	ICMC	2017	DBLP BibTeX RDF
12	Seongjong Kim, Joao Pedro Cerqueira, Mingoo Seok	Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation.	ESSCIRC	2017	DBLP DOI BibTeX RDF
12	Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael S. Floyd, Malcolm S. Ware, Gerard Salem, Sean M. Carey, Phillip J. Restle	26.2 Power supply noise in a 22nm z13™ microprocessor.	ISSCC	2017	DBLP DOI BibTeX RDF
12	Chen Sun 0003, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic	Microprocessor chip with photonic I/O.	OFC	2017	DBLP BibTeX RDF
12	Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre	Contrast of a HDL model and COTS version of a microprocessor for soft-error testing.	LATS	2017	DBLP DOI BibTeX RDF
12	Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra	Microprocessor Based Physical Unclonable Function.	iNIS	2017	DBLP DOI BibTeX RDF
12	Lukasz Przenioslo, Marcin Holub	Development of microprocessor, time optimized stepper motor driving algorithm.	MMAR	2017	DBLP DOI BibTeX RDF
12	Pawel Marzec, Pawel Fluder, Andrzej Kos	Measurement of microprocessor throughput increase with new control system.	MIXDES	2017	DBLP DOI BibTeX RDF
12	Pawel Fluder, Pawel Marzec, Andrzej Kos	Compact model of microprocessor cooling system based on ambient circumstanes.	MIXDES	2017	DBLP DOI BibTeX RDF
12	Riccardo Cantoro	New techniques for functional testing of microprocessor based systems.		2017	RDF
12	Wei Hu 0008, Armaiti Ardeshiricham, Ryan Kastner	Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities.	MTV	2017	DBLP DOI BibTeX RDF
12	Ahmed Wahba, Justin Hohnerlein, Farhan Rahman, Li-C. Wang	Dynamic Exerciser Template Weighting in x86 Processor Verification.	MTV	2017	DBLP DOI BibTeX RDF
12	Martin Fajcik, Pavel Smrz, Marcela Zachariásová	Automation of Processor Verification Using Recurrent Neural Networks.	MTV	2017	DBLP DOI BibTeX RDF
12	Mark Nelson 0004, Peter-Michael Seidel	Modeling and Analysis of Secure Processor Extensions Based on Actor Networks.	MTV	2017	DBLP DOI BibTeX RDF
12	Khaled Salah 0001	A Unified UVM Architecture for Flash-Based Memory.	MTV	2017	DBLP DOI BibTeX RDF
12	Jack Lawrence Mason	Validation of Context Preserving Thread-Level Speculative Execution Using N-Queens: Comparison of Non-CPSE and CPSE-enabled Applications.	MTV	2017	DBLP DOI BibTeX RDF
12	Anand Raman, Yorgos Koutsoyannopoulos, Magdy Abadir	Electromagnetic (EM) Crosstalk Failures and Symptoms in SoC Designs.	MTV	2017	DBLP DOI BibTeX RDF
12	Mikhail M. Chupilko, Alexander Kamkin, Artem Kotsynyak, Alexander Protsenko, Sergey A. Smolov, Andrei Tatarnikov	Maintaining ISA Specifications in MicroTESK Test Program Generator.	MTV	2017	DBLP DOI BibTeX RDF
12	Madhukarreddy Pappireddy, Bipin Ravi	SequenceLanguage: A Constraint Random MP-RIS Generation Framework.	MTV	2017	DBLP DOI BibTeX RDF
12	Ahmed Abdel-Haleem, Magdy A. El-Moursy	TLM Virtual Platform for Fast and Accurate Power Estimation.	MTV	2017	DBLP DOI BibTeX RDF
12	Liting Yu, Xiaoxiao Wang 0001, Fahim Rahman, Mark M. Tehranipoor	iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement.	MTV	2017	DBLP DOI BibTeX RDF
12	Kaushik Gopalakrishnan, Bipin Ravi	Anvil: Best in Class Multiprocessor Coherency Verification Tool.	MTV	2017	DBLP DOI BibTeX RDF
12	Fahim Rahman, Mohammad Farmani, Mark M. Tehranipoor, Yier Jin	Hardware-Assisted Cybersecurity for IoT Devices.	MTV	2017	DBLP DOI BibTeX RDF
12	Siroos Madani, Magdy A. Bayoumi	A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits.	MTV	2017	DBLP DOI BibTeX RDF
12	Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov	Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
12	Tiago Reimann, Cliff C. N. Sze, Ricardo Reis 0001	Challenges of cell selection algorithms in industrial high performance microprocessor designs.	Integr.	2016	DBLP DOI BibTeX RDF
12	Chang-Chih Chen, Taizhi Liu, Linda Milor	System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
12	Sai Manoj P. D., Hao Yu 0001, Hantao Huang, Dongjun Xu	A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF