Search results for "wiring"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell	Topological channel routing [VLSI].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	David W. Knapp	Fasolt: a program for feedback-driven data-path optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng	An H-V alternating router.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Oliver Collins, Sam Dolinar, Robert J. McEliece, Fabrizio Pollara	A VLSI Decomposition of the deBruijn Graph.	J. ACM	1992	DBLP DOI BibTeX RDF	deBruijn graphs, graph decomposition
9	Don L. Millard, Karl R. Umstadter, Robert C. Block	Noncontact Testing of Circuits Via a Laser-Induced Plasma Electrical Pathway.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
9	Tai-Ching Tuan, Kim-Heng Teo	On river routing with minimum number of jogs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
9	Colin M. Maunder, Rodham E. Tulloss	An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	ANSI/IEEE Std 1149.1, loaded-board test, self-test, boundary scan, JTAG
9	Boris Breznen	Transformation of Control Signals for Saccadic Eye Movements.	IWANN	1991	DBLP DOI BibTeX RDF
9	Jih-Shyr Yih, Pinaki Mazumder	A neural network design for circuit partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	Michael D. Osterman, Michael G. Pecht	Placement for reliability and routability of convectively cooled PWBs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	Michael C. McFarland, Thaddeus J. Kowalski	Incorporating bottom-up design into hardware synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	Ronald F. Ayres	Completely automatic completion of VLSI designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	M. J. Little, R. David Etchells, Jan Grinberg, S. P. Laub, J. G. Nash, M. W. Yung	The 3-D Computer.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
9	Chang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang	Path search on rectangular floorplan.	EURO-DAC	1990	DBLP DOI BibTeX RDF
9	Gabriele Saucier, Christopher Duff, Franck Poirot	State assignment of controllers for optimal area implementation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
9	Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Logic Synthesis for Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF
9	Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal	Segmented Channel Routing.	DAC	1990	DBLP DOI BibTeX RDF
9	Hong Cai, Ralph H. J. M. Otten	Conflict-free channel definition in building-block layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
9	Fadi J. Kurdahi, Alice C. Parker	Techniques for area estimation of VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
9	Gary D. Hachtel, Christopher R. Morrison	Linear complexity algorithms for hierarchical routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
9	B. Lokanathan, Edwin Kinnen	Performance optimized floor planning by graph planarization.	DAC	1989	DBLP DOI BibTeX RDF
9	C. C. Chen, S.-L. Chow	The Layout Synthesizer: An Automatic Netlist-to-Layout System.	DAC	1989	DBLP DOI BibTeX RDF
9	P. Groenveld	On Global Wire Ordering for Macro-Cell Routing.	DAC	1989	DBLP DOI BibTeX RDF
9	Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli	ORCA a Sea-of-Gates Place and Route System.	DAC	1989	DBLP DOI BibTeX RDF
9	Elizabeth D. Lagnese, Donald E. Thomas	Architectural Partitioning for System Level Design.	DAC	1989	DBLP DOI BibTeX RDF
9	Jih-Shyr Yih, Pinaki Mazumder	A Neural Network Design for Circuit Partitioning.	DAC	1989	DBLP DOI BibTeX RDF
9	Jian-Ning Song, Yun-Kang Chen	Two-stage channel routing for CMOS gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
9	Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner	CAPCAL-a 3-D capacitance solver for support of CAD systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
9	Takao Asano	Generalized Manhattan path algorithm with applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
9	Yoichi Shiraishi, Jun'ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh	A High Packing Density Module Generator for CMOS Logic Cells.	DAC	1988	DBLP BibTeX RDF
9	Paul Molitor	On the Contact-Minimization-Problem.	STACS	1987	DBLP DOI BibTeX RDF
9	Keith Waters	A muscle model for animation three-dimensional facial expression.	SIGGRAPH	1987	DBLP DOI BibTeX RDF
9	Edward J. DeJesus, James P. Callan, Curtis R. Whitehead	PEARL: an expert system for power supply layout.	DAC	1986	DBLP DOI BibTeX RDF
9	R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby	Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning.	DAC	1986	DBLP DOI BibTeX RDF	SPICE
9	Michael C. McFarland	Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions.	DAC	1986	DBLP DOI BibTeX RDF
9	Kjell Bratbergsengen, Rune Larsen 0001, Oddvar Risnes, Terje Aandalen	A Neighbor Connected Processor Network for Performing Relational Algebra Operations.	Computer Architecture for Non-Numeric Processing	1980	DBLP DOI BibTeX RDF
9	G. Jack Lipovski	An organization for optical linkages between integrated circuits.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
9	J. S. Mamelak	The Placement of Computer Logic Modules.	J. ACM	1966	DBLP DOI BibTeX RDF