Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Brian W. Curran, Lee Eisen, Eric M. Schwarz, Pak-kin Mak, James D. Warnock, Patrick J. Meaney, Michael F. Fee	The zEnterprise 196 System and Microprocessor.	IEEE Micro	2011	DBLP DOI BibTeX RDF
12	Ru Wang, Bao-Xia Fan, Liang Yang, Yan-Ping Gao, Dong Liu, Bin Xiao 0006, Jiang-Mei Wang, Yifu Zhang, Hong Wang, Weiwu Hu	Physical Implementation of the Eight-Core Godson-3B Microprocessor.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
12	Zichu Qi, Hui Liu, Xiangku Li, Weiwu Hu	Design for Testability Features of Godson-3 Multicore Microprocessor.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
12	Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez	Design methodology for the IBM POWER7 microprocessor.	IBM J. Res. Dev.	2011	DBLP DOI BibTeX RDF
12	Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar	Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
12	Ruey-Fong Chang, Chen-Wei Chang, Kuo-Hsiung Tseng, Cheng-Lun Chiang, Wen-Shiow Kao, Wen-Jang Chen	Structural planning and implementation of a microprocessor-based human-machine interface in a steam-explosion process application.	Comput. Stand. Interfaces	2011	DBLP DOI BibTeX RDF
12	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy.	ACM Trans. Archit. Code Optim.	2011	DBLP DOI BibTeX RDF
12	Marek Chrobak, Christoph Dürr, Mathilde Hurand, Julien Robert	Algorithms for temperature-aware task scheduling in microprocessor systems.	Sustain. Comput. Informatics Syst.	2011	DBLP DOI BibTeX RDF
12	Ihab Sbeity, Mohamed Dbouk, Brigitte Plateau	Stochastic bounds for microprocessor systems availability.	Int. Arab J. Inf. Technol.	2011	DBLP BibTeX RDF
12	Georgios N. Selimis, Li Huang, Fabien Massé, Ioanna Tsekoura, Maryam Ashouei, Francky Catthoor, Jos Huisken, Jan Stuyt, Guido Dolmans, Julien Penders, Harmke de Groot	A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design.	J. Medical Syst.	2011	DBLP DOI BibTeX RDF
12	Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty	Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
12	Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2011	DBLP DOI BibTeX RDF
12	Bartomeu Alorda, Kay Suenaga, Pere Pons	Design and evaluation of a microprocessor course combining three cooperative methods: SDLA, PjBL and CnBL.	Comput. Educ.	2011	DBLP DOI BibTeX RDF
12	Yoji Bando, Makoto Nagata	Microprocessor power noise measurements with different levels of resource occupancy.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
12	Meeta Sharma Gupta, Pradip Bose	Variation-Tolerant Microprocessor Architecture at Low Power.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
12	Magdy S. Abadir, Jay Bhadra, Li-C. Wang (eds.)	12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011	MTV	2011	DBLP BibTeX RDF
12	Wei Jin 0004, Sheng Lu, Weifeng He, Zhigang Mao	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
12	Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst	Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach.	PPES	2011	DBLP DOI BibTeX RDF
12	Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González 0001	Accelerating microprocessor silicon validation by exposing ISA diversity.	MICRO	2011	DBLP DOI BibTeX RDF
12	Andrzej Kwiecien, Michal Mackowski, Krzysztof Skoroniak	The Analysis of Microprocessor Instruction Cycle.	CN	2011	DBLP DOI BibTeX RDF
12	Andrzej Kwiecien, Michal Mackowski, Krzysztof Skoroniak	Instruction Prediction in Microprocessor Unit.	CN	2011	DBLP DOI BibTeX RDF
12	Nai-Fu Chang, Cheng-Yi Chiang, Tung-Chien Chen, Liang-Gee Chen	Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor.	EMBC	2011	DBLP DOI BibTeX RDF
12	Patrick J. Eibl, Albert Meixner, Daniel J. Sorin	An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2.	SIGMETRICS	2011	DBLP DOI BibTeX RDF
12	Florent de Dinechin	The Arithmetic Operators You Will Never See in a Microprocessor.	IEEE Symposium on Computer Arithmetic	2011	DBLP DOI BibTeX RDF
12	Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze	Grid-to-ports clock routing for high performance microprocessor designs.	ISPD	2011	DBLP DOI BibTeX RDF
12	Assen V. Krumov	Maximum torque high efficiency microprocessor based control of induction motors.	MIPRO	2011	DBLP BibTeX RDF
12	Nathan Ickes, Yildiz Sinangil, Francesco Pappalardo 0002, Elio Guidetti, Anantha P. Chandrakasan	A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip.	ESSCIRC	2011	DBLP DOI BibTeX RDF
12	Friedrich Bauer, Joseph Wenninger, Jan Haase 0001, Thomas Fischer 0012	Watching a processor at work: A self-explanatory simulator and illustrator for the MC8 microprocessor.	EUROCON	2011	DBLP DOI BibTeX RDF
12	Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian	Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus.	ICCAD	2011	DBLP DOI BibTeX RDF
12	James D. Warnock, Y. Chan, William V. Huott, Sean M. Carey, Michael F. Fee, Huajun Wen, Mary Jo Saccamango, Frank Malgioglio, Patrick J. Meaney, Donald W. Plass, Yuen H. Chan, Mark D. Mayo, Guenter Mayer, Leon J. Sigal, David L. Rude, Robert M. Averill III, Michael H. Wood, Thomas Strach, Howard H. Smith, Brian W. Curran, Eric M. Schwarz, Lee Eisen, Doug Malone, Steve Weitzel, Pak-kin Mak, Thomas J. McPherson, Charles F. Webb	A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.	ISSCC	2011	DBLP DOI BibTeX RDF
12	Kris Myny, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans	An 8b organic microprocessor on plastic foil.	ISSCC	2011	DBLP DOI BibTeX RDF
12	Youngtaek Kim, Lizy Kurian John	Automated di/dt stressmark generation for microprocessor power delivery networks.	ISLPED	2011	DBLP BibTeX RDF
12	Ron Zeira, Dmitry Korchemny, Ron Shamir	Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing.	Haifa Verification Conference	2011	DBLP DOI BibTeX RDF
12	Tae Houn Song, Soonmook Jeong, Seunghun Jin, Dongkyun Kim, Key Ho Kwon, Jae Wook Jeon	A System Consisting of Off-Chip Based Microprocessor and FPGA Interface for Human-Robot Interaction Applications.	ICCSA (5)	2011	DBLP DOI BibTeX RDF
12	V. Om Prakash Rai, D. R. Mehta, S. K. Parganiha	External interrupt verification for microprocessor design.	ICWET	2011	DBLP DOI BibTeX RDF
12	Kourosh Sedghisigarchi	A microprocessor-based controller for high temperature PEM fuel cells.	IAS	2011	DBLP DOI BibTeX RDF
12	Salma Bergaoui, Régis Leveugle	Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System.	DELTA	2011	DBLP DOI BibTeX RDF
12	Michael J. Anderson, Bryan Catanzaro, Jike Chong, Ekaterina Gonina, Kurt Keutzer, Chao-Yue Lai, Mark Murphy, David Sheffield, Bor-Yiing Su, Narayanan Sundaram	Considerations When Evaluating Microprocessor Platforms.	HotPar	2011	DBLP BibTeX RDF
12	Qi Guo 0001, Tianshi Chen 0002, Yunji Chen, Zhi-Hua Zhou, Weiwu Hu, Zhiwei Xu 0002	Effective and Efficient Microprocessor Design Space Exploration Using Unlabeled Design Configurations.	IJCAI	2011	DBLP DOI BibTeX RDF
12	Vivek S. Nandakumar, Malgorzata Marek-Sadowska	Layout effects in fine grain 3D integrated regular microprocessor blocks.	DAC	2011	DBLP DOI BibTeX RDF
12	Christoph Wolf, Steffen Zeidler 0001, Milos Krstic, Rolf Kraemer	Overview on ATE Test and Debugging Methods for Asynchronous Circuits.	MTV	2011	DBLP DOI BibTeX RDF
12	Daecheol You, Young-Si Hwang, Youngho Ahn, Ki-Seok Chung	A Test Method for Power Management of SoC-based Microprocessors.	MTV	2011	DBLP DOI BibTeX RDF
12	Alper Sen 0001, Etem Deniz	Verification Tests for MCAPI.	MTV	2011	DBLP DOI BibTeX RDF
12	Devraj Kallappa Bakchowde, Nanda Kishore AS	An Efficient Overlapping Event Generation Method for Symmetric System Testing.	MTV	2011	DBLP DOI BibTeX RDF
12	Ernesto Sánchez 0001, Giovanni Squillero, Alberto Paolo Tonda	Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification.	MTV	2011	DBLP DOI BibTeX RDF
12	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Reusing of Properties after Discretization of Hybrid Automata.	MTV	2011	DBLP DOI BibTeX RDF
12	Mona Safar, Magdy A. El-Moursy, Ashraf Salem, Mohamed Abdelsalam	TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.	MTV	2011	DBLP DOI BibTeX RDF
12	Christian Miller, Karina Gitina, Bernd Becker 0001	Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.	MTV	2011	DBLP DOI BibTeX RDF
12	Sergey Sofer, Asher Berkovitz, Valery Neiman	High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches.	MTV	2011	DBLP DOI BibTeX RDF
12	Kesava R. Talupuru, Sanjai Athi	Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking.	MTV	2011	DBLP DOI BibTeX RDF
12	Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula	A Unified Formal Framework for Analyzing Functional and Speed-path Properties.	MTV	2011	DBLP DOI BibTeX RDF
12	Ouiza Dahmoune, Robert de B. Johnston	Model Checker to FPGA Prototype Commmunication Bottleneck Issue.	MTV	2011	DBLP DOI BibTeX RDF
12	Gabriel H. Loh, Yuan Xie 0001	3D Stacked Microprocessor: Are We There Yet?	IEEE Micro	2010	DBLP DOI BibTeX RDF
12	Bao-Xia Fan, Liang Yang, Jiang-Mei Wang, Ru Wang, Bin Xiao 0006, Ying Xu, Dong Liu, Ji-Ye Zhao	Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor.	J. Comput. Sci. Technol.	2010	DBLP DOI BibTeX RDF
12	Ji-Ye Zhao, Dong Liu, Dan-Dan Huan, Meng-Hao Su, Bin Xiao, Ying Xu, Feng Shi, Chen Chen, Song Wang	Physical Design Methodology for Godson-2G Microprocessor.	J. Comput. Sci. Technol.	2010	DBLP DOI BibTeX RDF
12	Xi Chen 0068, Lei Yang 0017, Robert P. Dick, Li Shang, Haris Lekatsas	C-Pack: A High-Performance Microprocessor Cache Compression Algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
12	Zbigniew Stachniak	The MIL MF7114 Microprocessor.	IEEE Ann. Hist. Comput.	2010	DBLP DOI BibTeX RDF
12	Jacek Izydorczyk, Michal Izydorczyk	Microprocessor Scaling: What Limits Will Hold?.	Computer	2010	DBLP DOI BibTeX RDF	Information theory, Hardware, Integrated circuit design, CMOS technology, Moore's law
12	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Adaptive Pipeline voltage Scaling in High Performance Microprocessor.	J. Circuits Syst. Comput.	2010	DBLP DOI BibTeX RDF
12	Bruno Osorno	Analysis of Microprocessor Based Protective Re-lay's (MBPR) Differential Equation Algorithms	CoRR	2010	DBLP BibTeX RDF
12	Peter van Stralen, Andy D. Pimentel	A High-level Microprocessor Power Modeling Technique Based on Event Signatures.	J. Signal Process. Syst.	2010	DBLP DOI BibTeX RDF
12	Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, Matteo Sonza Reorda	Microprocessor Software-Based Self-Testing.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF
12	David S. Hardin (eds.)	Design and Verification of Microprocessor Systems for High-Assurance Applications.		2010	DBLP DOI BibTeX RDF
12	Magdy S. Abadir, Jay Bhadra, Li-C. Wang (eds.)	11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010	MTV	2010	DBLP BibTeX RDF
12	Chee-Kong Chui	The LogP and MLogP models for parallel image processing with multi-core microprocessor.	SoICT	2010	DBLP DOI BibTeX RDF
12	Yang Liu 0029, Jon Timmis, Omer Qadir, Gianluca Tempesti, Andy M. Tyrrell	A Developmental and Immune-Inspired Dynamic Task Allocation Algorithm for Microprocessor Array Systems.	ICARIS	2010	DBLP DOI BibTeX RDF
12	Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Eduardo H. Pacheco, Murli Tirumala	General behavioral thermal modeling and characterization for multi-core microprocessor design.	DATE	2010	DBLP DOI BibTeX RDF
12	Tao Zhang, Tao Lv 0001, Xiaowei Li 0001	An abstraction-guided simulation approach using Markov models for microprocessor verification.	DATE	2010	DBLP DOI BibTeX RDF
12	Songjun Pan, Yu Hu 0001, Xiaowei Li 0001	IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults.	DATE	2010	DBLP DOI BibTeX RDF
12	Michal Mackowski, Krzysztof Skoroniak	Instruction Prediction in Microprocessor Unit Based on Power Supply Line.	CN	2010	DBLP DOI BibTeX RDF
12	Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese	Microprocessor fault-tolerance via on-the-fly partial reconfiguration.	ETS	2010	DBLP DOI BibTeX RDF
12	Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz	Scan based speed-path debug for a microprocessor.	ETS	2010	DBLP DOI BibTeX RDF
12	Harold W. Cain, Priya Nagpurkar	Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.	ISPASS	2010	DBLP DOI BibTeX RDF
12	Xinfeng Xu, Yong Hei	New Trends in Microprocessor Architecture for Parallel Computing.	FCST	2010	DBLP DOI BibTeX RDF
12	Giang Nguyen Huong, Seon Wook Kim	Support of cross calls between a microprocessor and FPGA in CPU-FPGA coupling architecture.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
12	Keith A. Bowman, James W. Tschanz	Resilient microprocessor design for improving performance and energy efficiency.	ICCAD	2010	DBLP DOI BibTeX RDF
12	Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.	CICC	2010	DBLP DOI BibTeX RDF
12	James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.	ISSCC	2010	DBLP DOI BibTeX RDF
12	Mondira (Mandy) Deb Pant	Microprocessor power delivery challenges in the Nano-Era.	ISLPED	2010	DBLP DOI BibTeX RDF	power delivery, power, microprocessors
12	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
12	Václav Dvorák	Multi-Terminal BDDs in Microprocessor-based Control.	ICINCO (3)	2010	DBLP BibTeX RDF
12	Tatsuya Suto, Kenji Ichijo, Yoshio Yoshioka	Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System.	DFT	2010	DBLP DOI BibTeX RDF
12	Rajesh Kannan Megalingam, V. Krishnan, M. Nair, Vineeth Sarma V., Rahul Srikumar	Serializing the data bus of the Sun OpenSPARC T1 microprocessor datapath for reduced power consumption.	ICWET	2010	DBLP DOI BibTeX RDF
12	Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	Adaptive power gating for function units in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
12	Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska	Statistical static timing analysis flow for transistor level macros in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
12	Warren A. Hunt Jr.	Verifying VIA Nano microprocessor components.	FMCAD	2010	DBLP BibTeX RDF
12	Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash	Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor.	ITC	2010	DBLP DOI BibTeX RDF
12	James Crafts, David Bogdan, Dennis Conti, Donato O. Forlenza, Orazio P. Forlenza, William V. Huott, Mary P. Kusko, Edward Seymour, Timothy Taylor, Brian Walsh	Testing the IBM Power 7™ 4 GHz eight core microprocessor.	ITC	2010	DBLP DOI BibTeX RDF
12	Rance Rodrigues, Sandip Kundu, Omer Khan	Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor.	ITC	2010	DBLP DOI BibTeX RDF
12	David Iverson, Dan Dickinson, John Masson, Christina Newman-LaBounty, Daniel Simmons, William Tanona	Redundant core testing on the cell BE microprocessor.	ITC	2010	DBLP DOI BibTeX RDF
12	Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen	The scan-DFT features of AMD's next-generation microprocessor core.	ITC	2010	DBLP DOI BibTeX RDF
12	Yongwen Wang, Qianbing Zheng, Qiang Dou, Minxuan Zhang	Low Power Design for a Multi-core Multi-thread Microprocessor.	GreenCom/CPSCom	2010	DBLP DOI BibTeX RDF
12	Brian W. Thompto, Bodo Hoppe	Verification for fault tolerance of the IBM system z microprocessor.	DAC	2010	DBLP DOI BibTeX RDF	CFI, error detection, fault injection, error recovery, SER, RAS
12	Daniel Jones 0005	High speed simulation of microprocessor systems using LTU dynamic binary translation.		2010	RDF
12	Danilo Ravotto	Analysis and development of methodologies for advanced microprocessor design support.		2010	RDF
12	Ouiza Dahmoune, Robert de B. Johnston	An Embedded Reachability Analyzer and Invariant Checker (ERAIC).	MTV	2010	DBLP DOI BibTeX RDF
12	Christian Miller, Karina Gitina, Christoph Scholl 0001, Bernd Becker 0001	Bounded Model Checking of Incomplete Networks of Timed Automata.	MTV	2010	DBLP DOI BibTeX RDF
12	Brian Keng, Andreas G. Veneris, Sean Safarpour	An Automated Framework for Correction and Debug of PSL Assertions.	MTV	2010	DBLP DOI BibTeX RDF
12	Oscar Ballan, Paolo Bernardi, Giovanni Fontana, Michelangelo Grosso, Ernesto Sánchez 0001	A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip.	MTV	2010	DBLP DOI BibTeX RDF
12	Devraj Kallappa Bakchowde, Nanda Kishore A. S.	An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated Peripherals.	MTV	2010	DBLP DOI BibTeX RDF