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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 42 occurrences of 35 keywords
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Results
Found 45 publication records. Showing 45 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey |
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 638-643, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha |
86 | Zarka Cvetanovic, Richard E. Kessler |
Performance analysis of the Alpha 21264-based Compaq ES40 system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 192-202, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
51 | Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson |
Testability access of the high speed test features in the Alpha 21264 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 487-495, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
51 | Michael K. Gowan, Larry L. Biro, Daniel B. Jackson |
Power Considerations in the Design of the Alpha 21264 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 726-731, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
48 | Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger |
Microprocessor pipeline energy analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 282-287, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
alpha 21264, over-provisioning, power, energy, speculation |
35 | Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas |
Hiding Synchronization Delays in a GALS Processor Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 159-169, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Juan L. Aragón, José González 0002, José M. García 0001, Antonio González 0001 |
Confidence Estimation for Branch Prediction Reversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 214-223, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Richard Weiss 0001, Nathan L. Binkert |
A Comparison of AES Candidates on the Alpha 21264. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AES Candidate Conference ![In: The Third Advanced Encryption Standard Candidate Conference, April 13-14, 2000, New York, New York, USA., pp. 75-81, 2000, National Institute of Standards and Technology,. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
33 | Richard E. Kessler |
The Alpha 21264 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 19(2), pp. 24-36, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Dilip K. Bhavsar |
An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 311-318, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Richard E. Kessler, Edward J. McLellan, D. A. Webb |
The Alpha 21264 microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 90-95, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell |
Timing verification of the 21264: A 600 MHz full-custom microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 96-103, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Daniel L. Leibholz, Rahul Razdan |
The Alpha 21264: a 500 MHz out-of-order execution microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: Proceedings IEEE COMPCON 97, San Jose, California, USA, February 23-26, 1997, Digest of Papers, pp. 28-36, 1997, IEEE Computer Society, 0-8186-7804-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
33 | Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan |
Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 16-24, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Yossi Malka, Avi Ziv |
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 644-649, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha |
17 | Cor Meenderinck, Ben H. H. Juurlink |
(When) Will CMPs Hit the Power Wall?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2008 Workshops - Parallel Processing, VHPC 2008, UNICORE 2008, HPPC 2008, SGS 2008, PROPER 2008, ROIA 2008, and DPA 2008, Las Palmas de Gran Canaria, Spain, August 25-26, 2008, Revised Selected Papers, pp. 184-193, 2008, Springer, 978-3-642-00954-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Sangeetha Sudhakrishnan, Liying Su, Jose Renau |
Processor Verification with hwBugHunt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 224-229, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Aamer Jaleel, Bruce L. Jacob |
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 559-574, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts |
17 | Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein |
Timing analysis for full-custom circuits using symbolic DC formulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1815-1830, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Aaron Smith, Jon Gibson, Bertrand A. Maher, Nicholas Nethercote, Bill Yoder, Doug Burger, Kathryn S. McKinley, James H. Burrill |
Compiling for EDGE Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA, pp. 185-195, 2006, IEEE Computer Society, 0-7695-2499-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein |
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 502-515, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Joon-Sang Park, Michael Penner, Viktor K. Prasanna |
Optimizing Graph Algorithms for Improved Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(9), pp. 769-782, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Cache-friendly algorithms, shortest path, graph algorithms, minimum spanning trees, graph matching, algorithm performance, cache-oblivious algorithms, data layout optimizations |
17 | Lu Peng 0001, Jih-Kwon Peir, Konrad Lai |
Signature Buffer: Bridging Performance Gap between Registers and Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 164-175, 2004, IEEE Computer Society, 0-7695-2053-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Peter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz 0001 |
SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 15 February 2004, Madrid, Spain, pp. 65-74, 2004, IEEE Computer Society, 0-7695-2061-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra |
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 458-463, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Christophe Lemuet, William Jalby, Sid Ahmed Ali Touati |
Improving Load/Store Queues Usage in Scientific Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 38-45, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | David Parello, Olivier Temam, Albert Cohen 0001, Jean-Marie Verdun |
Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 6-12 November 2004, Pittsburgh, PA, USA, CD-Rom, pp. 15, 2004, IEEE Computer Society, 0-7695-2153-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan |
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 234-239, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein |
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 70-75, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies |
Testability Features of the Alpha 21364 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 764-772, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Mondira Deb Pant, Pankaj Pant, D. Scott Wills |
On-chip decoupling capacitor optimization using architectural level prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(3), pp. 319-326, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Daniel A. Jiménez, Calvin Lin |
Neural methods for dynamic branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 20(4), pp. 369-397, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
neural networks, Branch prediction |
17 | Kazuto Matsuo, Jinhui Chao, Shigeo Tsujii |
An Improved Baby Step Giant Step Algorithm for Point Counting of Hyperelliptic Curves over Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANTS ![In: Algorithmic Number Theory, 5th International Symposium, ANTS-V, Sydney, Australia, July 7-12, 2002, Proceedings, pp. 461-474, 2002, Springer, 3-540-43863-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Joon-Sang Park, Michael Penner, Viktor K. Prasanna |
Optimizing Graph Algorithms for Improved Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Chi-Keung Luk, Robert Muth, Harish Patil, Richard Weiss 0001, P. Geoffrey Lowney, Robert S. Cohn |
Profile-guided post-link stride prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 167-178, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
address strides, post-link optimizations, profiling, data prefetching, memory latency |
17 | Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster |
Tradeoffs in power-efficient issue queue design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 184-189, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue |
17 | Daniel A. Jiménez, Heather L. Hanson, Calvin Lin |
Boolean Formula-Based Branch Prediction for Future Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 97-106, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Christopher T. Weaver, Todd M. Austin |
A Fault Tolerant Approach to Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 1-4 July 2001, Göteborg, Sweden, Proceedings, pp. 411-420, 2001, IEEE Computer Society, 0-7695-1101-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Aamer Jaleel, Bruce L. Jacob |
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 282-293, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Dilip K. Bhavsar, Rishan Tan |
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 385-390, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | R. Iris Bahar, Srilatha Manne |
Power and energy reduction via pipeline balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 218-229, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Lisa Wu 0001, Christopher T. Weaver, Todd M. Austin |
CryptoManiac: a fast flexible architecture for secure communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 110-119, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Kazumaro Aoki, Fumitaka Hoshino, Tetsutaro Kobayashi |
A Cyclic Window Algorithm for ECC Defined over Extension Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, Third International Conference, ICICS 2001, Xian, China, November 13-16, 2001, pp. 62-73, 2001, Springer, 3-540-42880-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Roberto Maro, Yu Bai 0001, R. Iris Bahar |
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 97-111, 2000, Springer, 3-540-42329-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power, high-performance, architecture-level |
17 | Kourosh Gharachorloo, Madhu Sharma, Simon Steely, Stephen Van Doren |
Architecture and design of AlphaServer GS320. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000., pp. 13-24, 2000, ACM Press, 1-58113-317-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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