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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 5 publication records. Showing 5 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
46 | Alberto Delmas Lascorz, Mostafa Mahmoud, Ali Hadi Zadeh, Milos Nikolic 0002, Kareem Ibrahim, Christina Giannoula, Ameer Abdelhadi, Andreas Moshovos |
Atalanta: A Bit is Worth a "Thousand" Tensor Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS (2) ![In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024, pp. 85-102, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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33 | Mohamed Shalan, Vincent John Mooney III |
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 79-84, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management |
33 | Albrecht P. Stroele, Frank Mayer |
Methods to reduce test application time for accumulator-based self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 48-53, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation |
30 | Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay |
Flip-flop chaining architecture for power-efficient scan during test application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 410-413, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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30 | Santanu Chattopadhyay, Naveen Choudhary |
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 552-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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