Search results for "Baugh-Wooley"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
152	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
113	Steve Hung-Lung Tu, Chih-Hung Yen	A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
91	Amir Khatibzadeh, Kaamran Raahemifar	A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier.	IWSOC	2005	DBLP DOI BibTeX RDF
68	K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana	Capricious Digital Filter Design and Implementation Using Baugh-Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
68	Franc Grootjen, Nikolai Schauer	Baugh-Wooley Multiplication for the RISCV Processor.	CoRR	2023	DBLP DOI BibTeX RDF
68	Ananda Kiran, Navdeep Prashar	FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic.	CoRR	2015	DBLP BibTeX RDF
68	Rakesh Warrier, Chan Hua Vun, Wei Zhang 0012	A low-power pipelined MAC architecture using Baugh-Wooley based multiplier.	GCCE	2014	DBLP DOI BibTeX RDF
68	Jin-Hao Tu, Lan-Da Van	Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
68	Abhijit R. Asati, Chandrashekhar	An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style.	ICIIS	2008	DBLP DOI BibTeX RDF
68	Magnus Själander, Per Larsson-Edefors	High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.	ICECS	2008	DBLP DOI BibTeX RDF
61	Abdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan	Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths.	ReConFig	2008	DBLP DOI BibTeX RDF	2D pipeline, Baugh-Wooley, Reconfigurable, Multiplier, distributed arithmetic, Systolic
61	Nuno Bandeira, Ken Vaccaro, James A. Howard	A Two's Complement Array Multiplier Using True Values of the Operands.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Pezaris multiplier, Baugh-Wooley multiplier, celluar-subtractor multiplier, Array multiplier, parallel multiplier, binary multiplication
46	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
46	Hayssam El-Razouk, Zine Abid	Area and Power Efficient Array and Tree Multipliers.	CCECE	2006	DBLP DOI BibTeX RDF
46	Humberto Calderon, Stamatis Vassiliadis	Reconfigurable universal SAD-multiplier array.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	sum of absolute differences, reconfigurable computing, partial reconfiguration, binary multiplication
46	Ahmed F. Shalash, Keshab K. Parhi	Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	LMS design, power efficient folding, wireline communications, traveling sales person, relaxed LMS, low power design, greedy algorithm, algorithm transformation
46	Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng	Design of a lower-error fixed-width multiplier for speech processing application.	ISCAS (3)	1999	DBLP DOI BibTeX RDF